Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
2002-06-24
2004-06-15
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
Reexamination Certificate
active
06750112
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method of forming a bitline and a bitline contact to a dynamic memory cell array, and a dynamic memory cell array having at least one bitline and a bitline contact manufactured by the method.
A schematic cross-sectional view of an exemplary single DRAM (Dynamic Random Access Memory) cell is shown in
FIG. 4
, wherein reference numeral
9
denotes a storage capacitor, reference numeral
10
denotes the source/drain region and reference numeral
18
denotes the gate electrode of a transistor. In
FIG. 4
, the storage capacitor
9
for storing information in the form of an electrical charge representing a logic value such as 0 or 1 is implemented as a trench capacitor. The trench capacitor is disposed in a trench
16
having a collar
11
preventing formation a parasitic capacitor, and having a surface strap
12
that also can be implemented as a buried strap so as to electrically connect the top electrode of the storage capacitor
9
with the source/drain region
10
of the transistor. A bitline
1
is connected via a bitline contact
2
with the source/drain region
10
of the transistor for reading the signal stored in the storage capacitor. The gate electrode
18
of the transistor is actuated by the wordline, which is not illustrated, to read the stored information from the capacitor
9
. In a DRAM cell array and, in particular, a so-called embedded DRAM cell array, additional metalization layers such as the M
1
metalization layer
15
are provided.
In the course of further development of DRAM cells and DRAM cell arrays, it has been attempted to increase the storage density of the memory cell array. As a condition of a further increase of the storage density, the area of the single memory cell has to shrink.
FIG. 6
shows the layout of an exemplary memory cell array implementing a so-called 8-F
2
-cell architecture. The array includes a storage trench capacitor and a planar transistor for each of the memory cells. For each of the memory cells, an area of 8F
2
is needed, wherein F denotes the smallest structural length that can be produced in the technology employed. The bitlines
1
are implemented as stripes and are extending parallel to each other, wherein the width as well as the distance between each of the bitlines amount to F, respectively. The word lines
6
each have a width as well as a distance to each other of F, respectively. The word lines
6
are disposed perpendicularly to the bitlines
1
. The active areas
13
of each of the memory cells are disposed beneath the bitlines
1
, and two wordlines
6
that are crossing each other above each of the active areas
13
. The active areas
13
are disposed at staggered positions to each other beneath neighboring bitlines
1
. A bitline contact
2
providing an electrical contact between the corresponding bitline
1
and the source/drain region
10
of the active area
13
is disposed in the middle of each of the active areas, respectively. The trenches
16
housing the trench capacitors
9
are disposed beneath the word lines
6
. A gate electrode
18
of the corresponding transistor is disposed at the crossing points between one of the bitlines
1
and one of the wordlines
6
within the active areas
13
.
The active areas
13
extend between two trenches
16
. Each of the active areas
13
includes two transistors, which are connected with the corresponding bitline
1
via a common bitline contact
2
. In dependence on the actuated wordline
6
, the corresponding storage capacitor
9
, which is disposed in one of the two trenches
16
, is read.
Usually, in commonly used DRAM cell arrays, the bitlines as well as the bitline contacts are made of tungsten, and they are separated from each other by a dielectric material such as silicon dioxide.
FIGS. 5A and 5B
illustrate the bitline and the bitline contact as manufactured by the prior-art dual damascene process.
FIG. 5A
shows a cross-section in a direction perpendicular to the wordlines
6
.
FIG. 5B
shows a cross-section in a direction parallel to the wordlines
6
.
In
FIGS. 5A and 5B
reference numeral
1
denotes a bitline, which forms part of the so-called M
0
metalization layer, whereas reference numeral
2
denotes a bitline contact extending to the source/drain region
10
of the underlying transistor. Between the wordlines
6
, a BPSG layer
3
is filled and planarized to provide an electrical insulation, and a first dielectric layer
4
. The first dielectric layer
4
is normally silicon dioxide deposited by the TEOS (tetraethylorthosilicate) process. The first dielectric layer
4
is provided to electrically insulate the bitline contacts
2
and the bitlines
1
from each other.
According to the dual damascene process, the first dielectric layer
4
is deposited on the surface of the BPSG layer
3
filling the space between the wordlines
6
. Then, a first photoresist material is applied, patterned to define the bitline contacts
2
, and, then, the bitline contacts
2
are etched into the first dielectric layer
4
. Afterward, the first photoresist material is removed. Next, a second photoresist material is applied and patterned to define the bitlines
1
. Then, the bitlines
1
are etched into the first dielectric layer
4
. In a following step, the second photoresist material is removed. Finally, the etched portions are filled with tungsten so as to provide the bitline contacts
2
and the bitlines
1
in one single step. Thereafter, a chemical mechanical polishing step is performed to remove the remaining tungsten material from the surface.
In the usually employed standard process of manufacturing DRAM cell arrays, next, a so-called retention anneal process is performed so as to remove crystal defects especially in the capacitor region of the DRAM cell whereby the retention time of the DRAM cell is set and, thus, the functionality of the DRAM cell is ensured. This retention anneal process is usually a furnace anneal process wherein the temperature is ramped up to temperatures higher than approximately 800° C.
Afterward, the other metalization layers such as the M
1
(metalization
1
) and the M
2
(metalization
2
) layers are deposited by known methods.
One problem associated with the conventionally employed bitlines made of tungsten is that the coupling of neighboring bitlines drastically increases with decreasing distances between them. This bitline coupling extremely reduces the device performance and thus is one of the most critical yield detractors in the shrinkage of DRAM cell size.
Hitherto, efforts have been made to increase the bitline layer thickness while at the same time reducing the line widths of the tungsten bitlines. Alternatively, it has been attempted to reduce the bitline coupling by twisting the bitlines at predetermined positions. Furthermore, it has been tried to improve the retention time of the DRAM cells by increasing the capacitance of the storage capacitor.
However, these measures have not given satisfactory results.
European Patent Application No. EP 0 730 298 A discloses a method of forming a bitline and a bitline contact. According to the method, after depositing a dielectric layer on the non-planarized surface of a DRAM memory cell array and forming a bitline contact, a wiring layer is formed. Subsequently, the second dielectric material is deposited and treated by a chemical mechanical polishing process to form a planarized surface. The second dielectric material is a low-k material, and the bitline contact is made of phosphorous-doped polysilicon.
In addition, International Publication Number WO 01/26139, which has a common assignee as the instant application, discloses a method of forming a bitline and a bitline contact. According to the method, the electrical contact between the bitlines and the source or drain portion of the DRAM cell is accomplished by first contact plugs of a conductive material, preferably polysilicon, and, additionally, by second contact plugs which are formed concurrently with bitlines in a dual damascene
Greenberg Laurence A.
Hoang Quoc
Infineon - Technologies AG
Mayback Gregory L.
Nelms David
LandOfFree
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