Method of forming a bit line over capacitor array of memory cell

Details Method of forming a bit line over capacitor array of memory cell Method of forming a bit line over capacitor array of memory cell

1992-02-19

1993-04-27

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 52, 437 60, 437228, H01L 21265, H01L 2170

Patent

active

052061833

ABSTRACT:
A method of forming a bit line over capacitor array of memory cells includes providing a first layer of polyimide over word lines. Such layer is then patterned and etched to define storage node circuits. A first layer of conductively doped polysilicon is applied over the first layer of polyimide. A second layer of polyimide is applied over the first layer of conductively doped polysilicon. The second layer of polyimide and first layer of polysilicon are etched over the first layer of polyimide to define isolated cell storage nodes. Such can be conducted without any prior patterning or masking of the second layer of polyimide and first layer of polysilicon. A third layer of polyimide is provided atop the wafer over the isolated cell storage nodes. The third and first layers of polyimide are etched to define bit line contacts. Insulating spacers are provided about the periphery within the bit line contacts. Conductive material is deposited to provide conductive material pillars within the bit line contacts. Remaining portions of the first, second and third layers of polyimide are etched from the wafer. A capacitor cell dielectric layer is provided atop the individual storage nodes. A capacitor cell polysilicon layer is provided atop the capacitor cell dielectric layer to define an array of memory cell capacitors. An insulating layer is provided atop the cell polysilicon later. An array of digit lines are provided atop the wafer which electrically connect with the conductive material pillars elevationally above the cell capacitors.

REFERENCES:
patent: 5061650 (1991-10-01), Dennison et al.
patent: 5138412 (1992-08-01), Hieda et al.

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