Method of forming a bilevel, self aligned, low base resistance s

Details Method of forming a bilevel, self aligned, low base resistance s Method of forming a bilevel, self aligned, low base resistance s

1992-09-25

1994-07-12

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 38, 437 55, 437 36, 437154, 148DIG10, 148DIG102, H01L 21265

Patent

active

053288572

ABSTRACT:
A semiconductor device is manufactured with precisely formed base and emitter regions. This is accomplished by arranging a plurality of insulator layer portions to form a plurality of windows. A dopant is then applied to the semiconductor device between the windows in order to accurately position emitter regions relative to base regions. In this manner a base of controlled dimensions can be formed. Thus the parasitic resistance of the base can be reduced and the figure of merit (emitter periphery/base area) can be increased.

REFERENCES:
patent: 4433470 (1984-02-01), Kameyama et al.
patent: 4433471 (1984-02-01), Ko et al.
patent: 4510016 (1985-04-01), Chi et al.
patent: 4539742 (1985-09-01), Kamzaki et al.
patent: 4625388 (1986-12-01), Rice
1992 Symposium on VLSI Technology, Digest of Technical Papers, Jun. 2, 1992, Seattle, pp. 54-55.

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