Method of forming a BiCMOS SOI wafer having thin and thick SOI r

Details Method of forming a BiCMOS SOI wafer having thin and thick SOI r Method of forming a BiCMOS SOI wafer having thin and thick SOI r

1992-05-15

1993-11-02

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 62, 437 90, 437 59, 437 51, 148DIG9, H01L 21265

Patent

active

052583180

ABSTRACT:
A SOI BiCMOS integrated circuit has CMOS devices formed in a thin epitaxial layer of 1,000 .ANG. and bipolar devices formed in a thick epitaxial layer of 1 .mu.m, the two thicknesses being formed by a process in which a set of oxide islands are formed on a first wafer; an epitaxial layer is grown from bipolar silicon regions up and over the islands in a step that forms the bottom portion of the bipolar regions; the first wafer is inverted and oxide-bonded to a second wafer with the newly grown epitaxial layer below the islands so that the new top surface has a high quality epitaxial layer; excess silicon is removed from the new surface and the surface is polished to a thickness of 1,000 .ANG. over the islands by use of a nitride polish stop layer, leaving a thick layer of epitaxial silicon of 1 .mu.m in the bipolar regions and a 1,000 .ANG. thick layer of epitaxial silicon in the CMOS regions.

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