Method of formation of bipolar transistor having reduced parasit

Details Method of formation of bipolar transistor having reduced parasit Method of formation of bipolar transistor having reduced parasit

1995-05-22

1997-04-29

Fourson, George

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Including passive device

H01L 21265

Patent

active

056248547

ABSTRACT:
Vertically stacked regions of n-type and p-type conductivity are formed around bipolar and field effect transistors to reduce parasitic capacitance between the semiconductor device and surrounding well regions. Under reverse bias a portion of the vertically stacked region is fully depleted and thus reduces the parasitic capacitance between the semiconductor device and the well region.

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