Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2003-11-07
2004-07-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S294000, C438S295000, C438S297000, C438S318000, C438S353000, C438S355000, C438S359000, C438S423000, C438S425000, C438S426000, C438S427000, C438S433000, C438S435000
Reexamination Certificate
active
06764922
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices and, more particularly, to semiconductor device shallow trench isolation (STI) structures and methods of forming such structures using oxynitride as the trench fill material to inhibit STI etch erosion during fabrication.
2. Background and Related Art
As the critical dimension (CD) of the polysilicon gate of field effect transistors (FETs) is made smaller in order to increase the performance of the FET, greater control of the gate CD is required. The variation in the gate CDs across the entire chip, known as across-chip-linewidth-variation (ACLV), is a determining factor in the overall circuit speed.
The typical method for patterning the polysilicon gate in ultra large scale integrated (ULSI) circuits is to use photolithography with small wavelength light (248 nm or smaller). In order to control the photolithography process, an anti-reflective coating is typically spun onto the blanket polysilicon film before the photoresist is spun on. The thickness of the anti-reflective coating is optimized such that a minimum amount of light is reflected from the substrate wafer. If the anti-reflective coating thickness varies across the chip, then the amount of reflected light will vary, which results in a lack of control of the photolithography process. This lack of control results in a larger ACLV and reduced circuit performance.
One of the key contributors to anti-reflective coating thickness variation across the chip is the height of the shallow trench isolation (STI) material relative to the silicon active area where the devices are located. After the gate-level mask and photolithography tools are optimized and the polysilicon etch process is optimized, STI height variation will be one of the remaining contributors to increased ACLV.
In typical semiconductor device manufacturing processes, the STI region is composed of a pure oxide material, such as high density plasma (HDP) oxide or plasma tetraethyl orthosilicate (TEOS). Since the STI trench formation and STI fill processes are performed at the beginning of the chip manufacturing process, the STI oxide encounters many subsequent wet etch processing steps (e.g. with dilute HF or buffered HF) as well as dry etching steps (e.g. reactive ion etching (RIE)). Thus, as a normal part of the fabrication process leading to the final device, the STI oxide will be etched away. This leads to a change in the height of the STI oxide compared to the silicon active area each of which exhibit height changes as the silicon wafer proceeds through the chip manufacturing process.
Since there are many etch steps between STI formation and polysilicon deposition, and each etching step has its associated variabilities, there is often a lack of control over the amount of etching the STI actually undergoes. In wet chemical baths, for example, the HF concentration is known to change over the life of the bath. Also, depending of the application technique used to administer the HF, there may also be within-wafer variations of the etching rate. Similarly, RIE tools, which typically process one wafer at a time, have well-known across wafer variations and wafer-to-wafer variations.
One way to reduce the erosion of the STI region is simply to eliminate as many wet and dry etch steps as possible between STI formation and deposition. For example, elimination of the sacrificial oxidation and oxide strip steps used to condition the active area surface provides some simplification. However, this approach can only be taken so far, as some of these steps may be necessary to create the final circuit and achieve necessary yield. Another way to reduce STI erosion is to reduce the amount of exposure to chemical etchants in each of the required etch steps. Likewise this approach is problematic, since the etchant steps are often made intentionally long to remove particulates, remedy inconsistent oxide thicknesses or create hydrogen-terminated surfaces for subsequent processes.
Other efforts have been made to form caps over the STI material in order to inhibit STI erosion during subsequent etching steps used to form the active areas. For example, U.S. Pat. No. 6,146,970 to Witek, et al. describes the use of a silicon nitride or nitrogen-rich silicon oxynitride layer for capping an oxide STI material such as TEOS. However, the Witek, et al. bilayer approach adds significant cost and process complexity to the formation of STI. For example, Witek, et al. use two separate liner processes, two separate deposition processes and two separate CMP processes.
In this regard, acceptable solutions to the erosion of STI must be simple and cost-effective. In addition to exhibiting simplicity and low cost, acceptable solutions should have sufficient robustness such that it is unnecessary to constrain other process variables simply to control STI height. At the same time, such solutions must preferably fit within existing processes so as to avoid affecting product yield and cost.
SUMMARY OF THE PRESENT INVENTION
Accordingly, it is an object of the present invention to provide improved semiconductor device structures and methods for making same.
It is a further object of the present invention to provide improved STI for semiconductor devices, such as, FETs.
It is yet a further object of the present invention to provide improved STI structures for USLI semiconductor devices and methods for making such structures.
It is still yet a further object of the present invention to provide an improved STI structure and a simple process for fabricating same, which structure and process provide improved fabrication control and, thus, improved device performance.
It is another object of the present invention to provide improved STI structures and methods of making same so as to control STI erosion and the height of the STI material relative to the semiconductor active area.
In accordance with the present invention, the STI between the active areas of semiconductor devices is formed of various structural arrangements of oxynitride. The oxynitride may be used for both the trench liner and trench fill material. Introducing nitrogen into both the oxide liner and plasma oxide fill material permits convenient utilization of existing processes. The oxynitride STI is formed in a manner to minimize stress to the surrounding silicon, and yet acts to provide an STI structure that resists etch attack and erosion during the required fabrication steps subsequent to the STI deposition.
Since the use of oxynitrides for STI results in minimal trench fill erosion, such use allows close control of STI height relative to the silicon active area across the wafer, and from wafer-to-wafer. Initially, a trench oxide liner may be nitrided by annealing, for example, in a nitrogen ambient to form an oxynitride liner. Then, the oxynitride STI fill material may be deposited directly into the trench during formation of the trench plug by the addition of nitrogen into the STI SiO
2
plasma trench fill process. The nitrogen concentration may be varied dynamically during the trench fill process so as to taylor it to the overall process. Varying the nitrogen concentration so that the highest concentration exists toward the surface of the plug minimizes both plug erosion and stress to the surrounding silicon under the active area regions.
These foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings, wherein like reference members represent like parts of the invention.
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patent: 61331
Beyer Klaus D.
Jamin Fen F.
Varekamp Patrick R.
International Business Machines - Corporation
Isaac Stanetta
Jordan John
Niebling John F.
Pepper Margaret A.
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