Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1997-04-14
1998-09-08
Chang, Joni
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438430, 438435, H01L 2176
Patent
active
058044906
ABSTRACT:
A method of isolation in silicon integrated circuit processing overfills the trench by a fill margin, deposits a temporary layer of poly having a thickness less than the trench depth by the thickness of an oxide polish stop, so that the top of the polish stop is coplanar with the top of the fill layer outside the trench; the temporary layer is polished outside the trench, using the fill layer and the polish stop layer as polish stops; the polish stop layer is removed together with the same thickness of the fill layer and temporary layer, preserving planarity that is destroyed by selectively etching the fill layer; the remaining temporary layer is stripped and a final touch up polish of the fill layer stops on the pad nitride.
REFERENCES:
patent: 4389294 (1983-06-01), Anantha et al.
patent: 4791073 (1988-12-01), Nagy et al.
patent: 5015602 (1991-05-01), Van Der Plas et al.
Fiegl Bernhard
Glashauser Walter
Levy Max G.
Nastasi Victor R.
Chang Joni
International Business Machines - Corporation
Siemens Aktiengesellschaft
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