Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
1999-12-13
2002-09-24
Arbes, Carl J. (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S840000, C029S846000
Reexamination Certificate
active
06453549
ABSTRACT:
FIELD OF THE INVENTION
This invention pertains to electronic packaging and, more particularly, to the fabrication of conductive holes or vias in an electronic package.
BACKGROUND OF THE INVENTION
In the manufacture of electronic packages such as printed circuit cards and boards (PCBs) used to carry integrated circuit chips, the vias or through holes are usually filled with organic materials organic hole fill is desirable for a number of reasons, and is achieved by using a soldermask or dielectric materials.
Recently, however, it has been discovered that conductive hole fill can be more advantageous. Upon completing the fabrication of plated through holes (PTHs) with plating of a desired metal thickness in the barrel, metal (copper) pins, or solid wires of desired thickness and length, are inserted into the PTHs. Where wires are used instead of pins, the wires must be cut.
In one embodiment, the surface of the package can be flash plated, in order to seal the pins/wires. Thereafter, a circuitization step is employed in order to fill the holes with metal.
The metal hole fill is more advantageous than is conductive paste with organic materials. One reason for this advantage is that the metal hole fill provides a lower coefficient of thermal expansion (CTE), closer to that of the substrate metals.
Filling the PTHs with metal alleviates the need for plating the holes. The copper or metal pins act as PTHs. This permits fabricating finer lines, since plated copper is eliminated. The procedure also eliminates post hole fill, and the necessity to remove soldermask-based hole fill materials. In addition, the concern of voiding in the PTH fill area is eliminated. Furthermore, the process itself is more efficient than are conventional processes,due to a reduction of waste and recycling costs associated with desmear, seed, plating, and post fill cleaning.
DISCUSSION OF RELATED ART
In U.S. Pat. No. 4,906,198, issued on Mar. 6, 1990, to Cosimano et al, for CIRCUIT BOARD ASSEMBLY AND CONTACT PIN FOR USE THEREIN, a printed circuit board having contact pins is illustrated. The contact pin provides an interference fit within one of the openings, and extends from the outer surface for electrical connection to external components. By contrast, the present invention seeks to provide a filling and seal for the vias and holes in the electronic package.
In U.S. Pat. No. 5,715,595, issued to Kman et al on Feb. 10, 1998 for METHOD OF FORMING A PINNED MODULE, an assembly having electrical pin connectors is shown. The patent describes a method of forming a pinned module. The pin is fitted into a PTH, and is crimped above the PTH surface. The remainder of the pin is attached to a second conductive PTH in a substrate.
In U.S. Pat. No. 5,543,586, issued to Crane, Jr. et al on Aug. 6, 1996 for APPARATUS HAVING INNER LAYERS SUPPORTING SURFACE-MOUNT COMPONENTS, a pin in a PTH is depicted with a fillet at the top of the pin. The pin is connected to an active device and is designed to support surface mounted components.
In U.S. Pat. No. 5,548,486, issued to Kman et al on Aug. 20, 1996 for PINNED MODULE, a pin is fitted into a PTH and the remainder of the pin is attached to another PTH.
In U.S. Pat. No. 5,479,319, issued to Werther on Dec. 26, 1995 for MULTI-LEVEL ASSEMBLIES FOR INTERCONNECTING INTEGRATED CIRCUITS, a multi-level assembly is shown. The substrates of the assembly are pinned together through their PTHs.
In U.S. Pat. No. 5,290,970, issued to Currie on Mar. 1, 1994 for MULTILAYER PRINTED CIRCUIT BOARD REWORK METHOD AND REWORK PIN, a multilayered PCB is illustrated. A rework method describes a pin that is pressed into a PTH.
In IBM disclosure nos. 34488 (RO892-0123) and 32604 (AT889-0674), repair/rework techniques are described that use pins disposed within PTHs, with subsequent resoldering.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a method for conductively filling a hole or via disposed upon an electronic package. Upon completing the fabrication of plated through holes (PTHs) of desired metal thickness in the barrel, metal (copper) pins or solid wires of desired thickness and length are inserted into the PTHs. Where wires are used instead of pins, the wires are cut. Using pins, one of the options is to flash plate the surface of the package in order to seal the pins. Thereafter, a circuitization step is employed in order to fill the holes with metal. The metal hole fill is more advantageous than that of conductive paste with organic materials. The metal hole fill provides a lower CTE, closer to that of the substrate metals.
It is an object of this invention to provide an improved method of filling PTHs in electronic packages.
It is another object of the invention to provide a method for conductively filling a hole or via of an electronic package by insertion of a pin or wire therein.
REFERENCES:
patent: 3385773 (1968-05-01), Frantzen
patent: 4562301 (1985-12-01), Kameda
patent: 4906198 (1990-03-01), Cosimano et al.
patent: 5259110 (1993-11-01), Bross et al.
patent: 5290970 (1994-03-01), Currie
patent: 5404637 (1995-04-01), Kawakami
patent: 5479319 (1995-12-01), Werther
patent: 5543586 (1996-08-01), Crane, Jr. et al.
patent: 5548486 (1996-08-01), Kman et al.
patent: 5715595 (1998-02-01), Kman et al.
patent: 6018866 (2000-02-01), Crudo et al.
patent: 6195883 (2001-03-01), Bhatt et al.
patent: 6272745 (2001-08-01), Kersten et al.
patent: 248239 (1987-07-01), None
patent: 4-10494q (1992-01-01), None
patent: 5-315762 (1993-11-01), None
I.B.M. Tech. Dicl. Bull vol. 34, No. 7A Dec. 1991, pp 416-418.*
IBM Disclosure #34488 (RO-892-0123) P.D. Isaacs and B.A. Towne, “Repair of Pad to Ball (or Column) on Solder Ball Column Pad-on-Via Opens”. Published in Research Disclosure, Dec. 1992, No. 344 Kenneth Mason Publications Ltd., England.
IBM Disclosure #32604 (AT889-0674) R.A. Foster, “Repair Technique for Area Array Solder Interconnections”. Published in Research Disclosure, Jun. 1991, No. 326 Kenneth Mason Publications Ltd., England.
Bhatt Anilkumar C.
Houser David E.
Welsh John A.
Arbes Carl J.
Fraley Lawrence R.
International Business Machines - Corporation
Salzman & Levy
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