Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2003-03-31
2004-11-02
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S426000, C438S430000, C438S431000, C438S435000, C438S699000, C438S701000, C438S703000, C438S723000, C438S724000, C438S752000, C438S787000, C438S791000, C438S933000
Reexamination Certificate
active
06812115
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of fabrication of integrated circuits, and, more particularly, to filling openings, such as trenches, with an insulating material to thereby form, for example, shallow trench isolation structures required in sophisticated integrated circuits.
2. Description of the Related Art
Modern integrated circuits comprise a huge number of circuit elements, such as resistors, capacitors, transistors and the like. Typically, these circuit elements are formed on and in a semiconductor layer, such as a silicon layer, wherein it is usually necessary to substantially electrically insulate adjacent semiconductor regions from each other, in which the individual circuit elements are formed. A representative example in this respect is a field effect transistor, the active area of which, i.e., the highly doped drain and source regions with an inversely lightly doped channel region disposed therebetween, is defined by an isolation structure formed in the semiconductor material.
Since critical feature sizes of the circuit elements, such as the gate length of field effect transistors, are steadily decreasing, the area enclosed by the isolation structures, as well as the isolation structures themselves, are also reduced in size. Among the various techniques for forming the isolation structures, the so-called shallow trench isolation (STI) technique has proven to be the most reliable method and has become the most frequently used technique for forming isolation structures for sophisticated integrated circuits.
According to the STI technique, individual circuit elements are insulated from each other by shallow trenches etched into the semiconductor material, i.e., a semiconductor substrate when bulk semiconductor devices are considered or a semiconductor layer formed on an insulating substrate as in the case, for example, for silicon-on-insulator (SOI) substrates, in which the circuit elements are to be formed. The trenches are subsequently filled with a dielectric material, such as an oxide, to provide the required electrical insulation of adjacent circuit elements. Although this technique has proven to be very reliable for the dimensions of trenches on the order of micrometers, reliability problems, such as increased leakage currents and the like, may arise for devices defined by sub-micron design rules, as will be explained in the following in more detail.
With reference to
FIGS. 1
a
-
1
f
, a typical conventional process flow for forming a shallow trench isolation will now be described. In
FIG. 1
a
, a semiconductor structure
100
comprises a substrate
101
that may include a semiconductor layer or that may be a semiconductor substrate, such as a silicon substrate, in and on which circuit elements, such as field effect transistors and the like, have to be formed. Moreover, a silicon dioxide layer
102
is formed on the substrate
101
followed by a silicon nitride layer
103
.
Typically, the silicon dioxide layer
102
is formed by thermally oxidizing the substrate
101
and, subsequently, the silicon nitride layer
103
is deposited by, for example, chemical vapor deposition (CVD), such as low pressure CVD (LPCVD). Subsequently, a layer of photoresist (not shown) is applied to the semiconductor structure
100
and is patterned by sophisticated photolithography and etch techniques in accordance with design requirements. In the example described herein, the trench isolation to be formed may be designed to have a width on the order of 0.25 &mgr;m or less and the photoresist layer is correspondingly patterned to serve as an etch mask for a subsequently performed anisotropic etch step.
FIG. 1
b
schematically shows the semiconductor structure
100
with a trench
104
formed in the silicon nitride layer
103
, the silicon dioxide layer
102
and partially in the substrate
101
. Typically, the trench
104
is etched with a depth of approximately 400-500 nm for the above specified width. Moreover, preferably, the anisotropic etch step for etching the silicon nitride layer
103
is designed to generate a tapered sidewall portion
105
that may promote the fill capability of a subsequent deposition step.
FIG. 1
c
schematically shows the semiconductor structure
100
during an initial stage of a deposition step to fill the trench
104
with silicon dioxide. In
FIG. 1
c
, a relatively thin silicon dioxide layer
106
is already formed on the silicon nitride layer
103
and inside the trench
104
. For depositing the silicon dioxide layer
106
into the trench
104
having dimensions of 0.25 &mgr;m and less, sophisticated deposition techniques have to be used to achieve a high degree of fullness in the trench
104
. Preferably, sub-atmospheric CVD deposition techniques are used for filling trenches having a width of 0.25 &mgr;m and sophisticated high density plasma-enhanced CVD deposition techniques may be used for a trench width less than 0.25 &mgr;m. Although these deposition techniques allow oncoming particles
107
to be deposited in a highly conformal manner within the trench
104
, the upper sidewall portions
105
, even though slightly tapered, will receive a thicker silicon dioxide layer during the ongoing deposition, since the number of oncoming particles
107
at corner portions
108
is higher than the number of particles
107
impinging on central sidewall portions
112
of the trench
104
.
FIG. 1
d
illustrates this situation, when the thickness of the silicon dioxide layer
106
has increased during the deposition so that the trench
104
is nearly closed at the corner portions
108
, thereby substantially preventing any further deposition of silicon dioxide within the trench
104
.
FIG. 1
e
schematically depicts the semiconductor structure
100
after completion of the deposition step, wherein a void
109
is formed within the trench
104
. Since the void
109
is highly undesirable for further processing of the semiconductor structure
100
, great efforts are made to at least reduce the size of the void
109
. To this end, the semiconductor structure
100
is heated in an oxidizing ambient to a temperature of approximately 900° C. to, on the one hand, to densify the silicon dioxide layer
106
and, on the other hand, to further oxidize silicon at the interface between the trench
104
and the substrate
101
, as indicated by the layer
110
. During this heat treatment, oxygen diffuses into the silicon dioxide layer
106
and thus into the trench
104
and leads to a further oxidation of the substrate
101
. Upon oxidation of the substrate
101
, stress is applied to the deposited silicon dioxide layer
106
within the trench
104
, since the newly grown silicon dioxide adjacent to the deposited silicon dioxide
106
occupies a larger volume than the silicon consumed by the oxidation process. In
FIG. 1
e
, the additional oxidized portion is indicated by
110
and the induced stress is indicated by arrows
111
.
FIG. 1
f
schematically depicts the semiconductor structure
100
after completion of the thermal oxidation process, wherein the void
109
in the lower portion of the trench
104
is removed by compressing the silicon dioxide
106
, so that a considerably smaller void
109
a
is formed in the vicinity of the upper portion of the trench
104
. As is evident from
FIG. 1
f
, substantially no stress is generated at the upper sidewall portions
105
of the non-oxidizable silicon dioxide layer
102
and the silicon nitride layer
103
.
FIG. 1
g
schematically shows the semiconductor structure
100
after planarizing the substrate
101
by chemically mechanically polishing (CMP) to remove the excess silicon dioxide
106
and partially remove the silicon nitride layer
103
, wherein the reduced void
109
a
is opening to form a groove-like recess that is, for convenience, also denoted by the reference number
109
a
. The CMP process for removing the excess oxide
106
and planarizing the substrate
101
is a critical step requiring thorough control of the remaining silicon nitride layer
1
Kruegel Stephan
Raab Michael
Wieczorek Karsten
Advanced Micro Devices , Inc.
Fourson George
García Joannie Adelle
Williams Morgan & Amerson P.C.
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