Method of fast testing of hot carrier effects

Details Method of fast testing of hot carrier effects Method of fast testing of hot carrier effects

1998-03-26

1999-12-07

Ballato, Josie

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

G01R 3126

Patent

active

059990112

ABSTRACT:
This invention describes a method for improving the test time for hot carrier injection effects in CMOS transistors. In conventional testing of hot carrier effects a stress voltage is applied between the drain and the source of a transistor. This stress voltage is limited by the drain to source punch-through voltage. In the enhance method described within, a substrate back bias is applied that extends the punch-through voltage and allows a higher drain to source stress voltage. With the higher stress voltage the amount of time needed to test parameter degradation caused by hot carrier injection is substantially reduced.

REFERENCES:
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patent: 5587665 (1996-12-01), Jiang
patent: 5598009 (1997-01-01), Bui
patent: 5600578 (1997-02-01), Fang et al.
patent: 5682051 (1997-10-01), Harrington, III
C.Y. Chang and S.M. Sze, "ULSI Technology", McGraw Hill, 1996, pp. 657-662. (No Month Available).

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