Method of fabrication of transistor device with increased breakd

Details Method of fabrication of transistor device with increased breakd Method of fabrication of transistor device with increased breakd

1993-01-22

1994-03-29

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437192, 437193, 437200, 148DIG96, 257557, H01L 21265

Patent

active

052984400

ABSTRACT:
A bipolar lateral device is disclosed having a high BV.sub.ceo. The device is formed according to a single polysilicon process. In one embodiment silicide is excluded from the surface of the N+ doped polysilicon protecting the N- base width region of the device and the resulting device has a BV.sub.ceo of 8 to 10 V. In another embodiment, the silicide is excluded from the surface of the polysilicon protecting the n-base width region and the polysilicon is maintained as intrinsic polysilicon. The resulting device has a BV.sub.ceo of about 20 V. The devices are useful as voltage clamping devices in programmable logic circuits which must withstand a collector to emitter reverse bias voltage that is sufficient to program either vertical fuse or lateral fuse devices.

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