Method of fabrication of stacked semiconductor devices

Details Method of fabrication of stacked semiconductor devices Method of fabrication of stacked semiconductor devices

1997-04-18

2000-12-26

Guay, John

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

438 33, 438 68, 438114, 438458, 438460, H01L 2150

Patent

active

061658154

ABSTRACT:
A method for increasing integrated circuit density comprising stacking an upper wafer and a lower wafer, each of which have fabricated circuitry in specific areas on their respective face surfaces. The upper wafer is attached back-to-back with the lower wafer with a layer of adhesive applied over the back side of the lower wafer. The wafers are aligned so as to bring complimentary circuitry on each of the wafers into perpendicular alignment. The adhered wafer pair is then itself attached to an adhesive film to immobilize the wafer during dicing. The adhered wafer pair may be die into individual die pairs or wafer portions containing more than one dice pair. At least one face side of the die pair (attachment side) may have an array of minute solder balls or small pins disposed thereon for attachment and electrical communication of the die to at least one substrate such as a printed circuit board or leadframe. The die pair face opposite the substrate attachment side (opposing side) and may have a plurality of bond pads. Bond wires or TAB leads are attached between bond pads on the opposing side and corresponding conductive trace or lead ends on the substrate. Alternately, both the attachment side and opposing side may have an array of minute solder balls or small pins for respective attachment to two facing substrates on opposite sides of the die pair.

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