Method of fabrication of semiconductor integrated circuit...

Details Method of fabrication of semiconductor integrated circuit... Method of fabrication of semiconductor integrated circuit...

2008-05-13

2008-05-13

Toatley, Jr., Gregory J. (Department: 2877)

Optics: measuring and testing

Inspection of flaws or impurities

C356S237400, C356S237500

Reexamination Certificate

active

07372555

ABSTRACT:
In the fabrication of a semiconductor integrated circuit device, a 2D-3D inspection technique for solder printed on a substrate is provided which permits easy preparation of data and easy visual confirmation of a defective portion. In a substrate inspecting step, first, a 3D inspection is performed, followed by execution of 2D inspection, whereby a 2D picked-up image of the portion of a pad determined to be defective can be displayed on a larger scale simultaneously with the end of inspection, thereby providing an environment for efficient visual confirmation of the defect. Further, by subjecting a raw substrate to measurement at the time of preparing inspection data, a relation between an original height measurement reference generated automatically by the inspection system and the height of a pad upper surface is checked, whereby it is possible to measure the height and volume of printed solder based on the pad upper surface.

REFERENCES:
patent: 6496270 (2002-12-01), Kelley et al.
patent: 2003/0001117 (2003-01-01), Hyun
patent: 2004/0184653 (2004-09-01), Baer et al.
patent: 2004/0213450 (2004-10-01), Okada et al.
patent: 2000-22326 (2000-01-01), None
patent: 2000-193432 (2000-07-01), None
Chinese Official Action for Application No. 200510006203.2, dated Jul. 20, 2007.

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