Method of fabrication of semiconductor device having a planar co

Fishing – trapping – and vermin destroying

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437 34, 437 41, 437 56, 437 58, 437203, 437193, 437 31, H01L 2122

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048031739

ABSTRACT:
An MOS device having a planar configuration in which the top surfaces of the source, drain and gate electrodes are coplanar, and the overlying electrical contact structure is also planar, is produced by a method of fabrication in which the gate is defined by forming an oxide mesa on a substrate, building up the substrate with semiconductor material around the mesa, removing the mesa, and filling the resultant trough with doped polysilicon to form the self-aligned gate. Line width and alignment control are enchanced. The planarity of the device and the improved dimensional control enable a reduction of device dimensions and consequently increased device density in integrated circuits.

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Johnson, "Self-Alignment Technique for Fabricating High-Performance FET's", IBBTDB vol. 15, No. 2, Jul. 1972, pp. 680-681.

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