Method of fabrication of protected programmable transistor with

Details Method of fabrication of protected programmable transistor with Method of fabrication of protected programmable transistor with

1994-10-28

1996-01-23

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 43, 437 52, 437 44, H01L 218247

Patent

active

054864801

ABSTRACT:
A programmable transistor includes impurity regions to reduce punch-through and soft-write phenomena. In order to provide a fast operation, the impurity regions are arranged with regard to one another so that parasitic capacitances at junctions of impurity regions of mutually opposite conductivity type are minimized. For these purposes, the transistor comprises a charge storage region over a channel region in a main semiconductor zone of a first conductivity type located between a source and a drain of a second conductivity type opposite to the first. A first impurity zone of the first conductivity type, substantially laterally contiguous with the drain, extends into the channel region and is more heavily doped than the main zone. The drain includes a heavily doped third impurity region and a lightly doped second impurity region that lies at least mainly between the third region and the zones.

REFERENCES:
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"A Reliable Profiled Lightly-Doped Drain (PLD) Cell for High Density Submicron EPROMS and Flash EEPROMS" by Yoshikawa, Extended Abstracts of 20th (1988) Conference on Solid State Devices and Materials, Aug. 24-26, 1988.
"A Flash-Erase EEPROM Cell With An Asymmetric Source and Drain Structure" by Kume et al., IEEE 1987, pp. 560-563.

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