Method of fabrication of MOS transistors having electrodes of me

Details Method of fabrication of MOS transistors having electrodes of me Method of fabrication of MOS transistors having electrodes of me

1987-01-12

1988-10-25

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437200, 437228, 148DIG51, 148DIG147, 357 67, 156657, H01L 2128

Patent

active

047804297

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The present invention relates to a method for fabrication of integrated circuits having a high integration density.
The integration density is higher as the dimensions of an elementary transistor are smaller. It is therefore sought to reduce these dimensions as far as possible without thereby impairing the electrical properties of the transistors produced.
Many parameters are to be taken into account in order to obtain good electrical properties. At least one of these parameters is particularly adversely affected by a reduction in dimensions and this parameter is the electrical conductivity of circuit connections, in particular the electrical conductivity of the leads which terminate at the gates, sources and drains of field-effect transistors. If the transistor is intended to be of very small size, the contacts of the source and drain electrodes with the source and drain regions will also be very small and, similarly, the gate must be very narrow. In that case, however, the ability of connections to transmit a high current density decreases, which is detrimental to good operation of the circuit.
It is for this reason that, whereas present-day industrial manufacturing processes make considerable use of polycrystalline silicon in the fabrication of the gate electrodes as well as the source and drain contacts and certain interconnections, it is being increasingly sought to cover the polycrystalline silicon with a layer of metallic silicide which has higher conductivity and substantially improves the overall conductivity of connections in respect of given dimensions of conductors. Furthermore, the present Applicant has endeavored to fabricate transistors in which polycrystalline silicon is not employed at all and in which the gate, source and drain electodes and the first-level interconnections are formed entirely of metallic silicide which is more conductive than the association of polycrystalline silicon and metallic silicide.
However, it is desirable under these conditions to provide fabrication processes which effectively permit a reduction in dimensions of transistors. In fact, if the use of metallic silicide were to impose fabrication processes which are not conducive to very small dimensions, there would be a risk of losing again any advantage which would have been gained in conductivity.
In other words, it is clearly desirable to reduce the resistivity of interconnections, of source and drain contacts and of gate electrodes but it is also desirable to benefit by this reduction in resistivity in order to increase the integration density of certain circuits or certain portions of circuits.
Another important aspect of the present invention arises from the fact that electrodes of metallic silicide which rests directly on monocrystalline silicon make it possible to establish Schottky-type (metal/semiconductor) contacts which offer an advantage in certain cases. The concept of field-effect transistors with Schottky contacts for the source and the drain is described in the article by M. P. Lepselter and S. M. Sze entitled "An insulated-gate field-effect transistor using Schottky barrier contacts as source and drain", published in "Proceedings of the IEEE, Vol. 56, August 1968, pages 1400-1402".
The technical problem presented by these Schottky transistors is the need to place the source contact (or drain contact) as close as possible to the gate, failing which a gap exists between the source proper (or the drain) and the gate-controlled channel, and the transistor cannot be made suitably conductive.


SUMMARY OF THE INVENTION

The present invention proposes a method of fabrication which makes it possible to place the source contact (or drain contact) much nearer to the gate, thereby making it possible not only to produce a Schottky-contact field-effect transistor in a convenient and efficient manner but also more generally to reduce the dimensions of transistors to a minimum, whether they are of the Schottky type or not.
The method of fabrication of field-effect transistors in ac

REFERENCES:
patent: 4539744 (1985-09-01), Burtan
patent: 4685196 (1987-08-01), Lee
patent: 4713356 (1987-12-01), Hirata
Tsang et al ". . . Sidewall Spacer Technology" IEEE J. Solid-State Circuits vol. SC-17 #2 Apr. 1982 pp. 220-226.
Ting, C. "Silicide for Contacts and Interconnects" IEDM Technical Digest 1984 pp. 110-113.
Higashika et al. "Sidwall Assisted . . . LSI's" Extended Abstracts of the 15th Conference on Solid State Devices and Materials 1983 pp. 69-72.

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