Fishing – trapping – and vermin destroying
Patent
1994-10-19
1996-08-27
Wilczewski, Mary
Fishing, trapping, and vermin destroying
437 52, 437 60, 437919, H01L 218247, H01L 2182
Patent
active
055500722
ABSTRACT:
An EEPROM cell is formed in an IC chip by using only three masking steps in addition to those required for the basic CMOS transistors in the chip. A first mask layer is used to define source/drain regions of select and memory transistors within the EEPROM cell; a second mask layer is used to define a tunneling region of the memory transistor;and a third mask layer is used to define a floating gate of the memory transistor and a gate of the select transistor. A control gate of the memory transistor is formed using the same mask that is used to define the gates of the CMOS transistors. The third and fourth mask layers may also be used to form the lower and upper electrodes, respectively, of a capacitor.
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Cacharelis Philip J.
Narahari Narasimha
Perry Jeffrey R.
Booth Richard A.
National Semiconductor Corporation
Steuber David E.
Wilczewski Mary
Winters Paul J.
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