Method of fabrication of insulated gate field effect semiconduct

Details Method of fabrication of insulated gate field effect semiconduct Method of fabrication of insulated gate field effect semiconduct

1972-06-23

1977-08-23

Rutledge, L. Dewayne

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

357 23, H01L 21316

Patent

active

040438481

ABSTRACT:
An insulated gate field effect transistor having a self-aligned gate, reduced capacitance, and lower surface step heights is fabricated with the use of a silicon nitride layer which serves first as a diffusion mask, than as an oxidation barrier, and ultimately as a gate dielectric. In an alternate embodiment, lower threshold voltages are achieved by replacing the initial gate dielectric with a thinner dielectric having a reduced surface state density.

REFERENCES:
patent: 3477886 (1969-11-01), Ehlenberger
patent: 3534234 (1970-10-01), Clevenger
patent: 3544858 (1970-12-01), Kooi
patent: 3597667 (1971-08-01), Horn

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