Method of fabrication of GaAs complementary enhancement mode jun

Details Method of fabrication of GaAs complementary enhancement mode jun Method of fabrication of GaAs complementary enhancement mode jun

1985-08-30

1987-07-14

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29577C, 29590, 29578, 148 15, 148186, 148DIG84, H01L 2100

Patent

active

046792988

ABSTRACT:
Ultra low-power GaAs complementary junction field effect transistors are implemented in the design of complementary integrated circuits using a planar technology in conjunction with multiple and selective ion implantation. Both junction FETs, namely the p and n channel devices, are enhancement mode devices and biased in the forward direction thus leading to the advantageous DCFL (directly coupled field effect transistor logic) with one power supply, low power dissipation and high packing densities, all prerequisites for VLSI (very large scale integration).

REFERENCES:
patent: 4452646 (1984-06-01), Zuleeg
patent: 4568957 (1986-02-01), Zuleeg et al.
Troeger et al, "Fully Ion Implanted Planar GaAs E-JFET Process", IEDM Tech. Dig, 1979, pp. 497-500.
Ghondi, VLSI Fabrication Principles Silicon and Gallium Arsenide, John Wiley & Sons, 1983, New York, pp. 593-595.
Troeger et al, "A Radiation-Hard Low-Power GaAs Static RAM Using E-JFET DCFL", GaAs IC Symp Tech. Dig., 1983, paper 20.
Zuleeg et al, "Femtojoule High-Speed Planar GaAs E-JFET Logic", IEEE Trans. Electron Devices, vol. ED-25, pp. 628-639, Jun. 1978.

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