Method of fabrication of dielectrically isolated CMOS devices

Details Method of fabrication of dielectrically isolated CMOS devices Method of fabrication of dielectrically isolated CMOS devices

1981-09-24

1983-11-22

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 29576E, 29576W, 148187, 148175, H01L 21265

Patent

active

044160500

ABSTRACT:
A method of fabricating an integrated circuit on a body of semiconductor material of a first conductivity type and a first dopant concentration by depositing a layer of semiconductor material of first conductivity type and a second dopant concentration on the body; etching the layer to form distinct silicon islands; depositing dopant species in predetermined ones of the silicon islands so that the major surface and exposed edges of ones of the islands becomes second conductivity type; and thermally oxidizing the exposed surface portions of the body so that oxide fills the regions between the silicon islands.

REFERENCES:
patent: 3966577 (1976-06-01), Hochberg
patent: 3983620 (1976-10-01), Spadea
patent: 4088516 (1978-05-01), Kondo et al.
patent: 4183134 (1980-01-01), Oehler et al.
patent: 4203126 (1980-05-01), Yim et al.
patent: 4263057 (1981-04-01), Ipri
patent: 4277883 (1981-07-01), Kaplan

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