Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
2002-01-30
2004-09-28
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S052000, C257S057000, C257S072000, C257S258000, C438S030000, C438S029000, C438S623000, C438S626000
Reexamination Certificate
active
06797983
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for fabricating a LCOS (liquid crystal on silicon) back plane, and more particularly to a method for fabricating a LCOS back plane structure, and application for the multimedia projector.
2. Description of the Prior Art
The CMOS (complementary metal oxide semiconductor) back plane of LCOS (liquid crystal on silicon) is an important electric device for the micro-display device.
In generally, the CMOS back plane structures constituted by LV CMOS transistor (low voltage complementary metal oxide semiconductor transistor) and an oxide capacitor layer. In the prior process for LV device, an oxide layer severs as a capacitor layer. Because the oxide layer merely sustains the low operating-voltage to limit the operating-voltage range, wherein the operating-voltage is under 5 volts. As if increasing the operating voltage, the area of the oxide capacitor layer is increased to sustain the higher voltage. However, the increased area of the oxide capacitor layer will increase the area the area of the integrated circuits. Therefore, the purpose of the semiconductor device has been densely integrated progressively, the element structure has been minimized cannot be achieved.
Furthermore, the oxide capacitor layer cannot sustain the higher voltage when increasing the operating voltage. After the operating voltage to the oxide capacitor layer during a period time, because the coupling ratio of the oxide capacitor layer is small, such that the breakdown of the oxide capacitor layer will be caused to lead the leakage current and the reliability of the integrated circuit will be reduced.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for fabricating a HV CMOS transistor (high voltage complementary metal oxide semiconductor transistor) back plane structure that substantially obtains the large operating voltage range and large operating capacitance range. This method essentially utilize a HV device is applied on the substrate, such that the LCOS (liquid crystal on silicon) back plane structure can obtain the large operating voltage and the HV device can cooperate with the HV capacitor layer that can sustain the higher operating voltage, and further generates the better capacitance operating range. Therefore, the LCOS back plane structure has the better contrast and the chrominance output in per area unit.
It is one object of this invention is that a HV device is applied to the substrate to obtain large operating voltage and better capacitance operating range.
It is another object of this invention is to utilize the mix mode IPD (inter-poly dielectric) structure that compatible with a HV CMOS transistor (high voltage complementary metal oxide semiconductor transistor) process, and also combined with a mirror layer to form a CMOS back plane of LCOS (liquid crystal on silicon) structure.
It is further object of this invention is to provide a HV transistor to drive the HV capacitor layer to obtain the large output operating voltage and better capacitance operating range.
It is still another object of this invention is to increase the output voltage to the mirror layer to obtain the best contrast and the output chrominance in per area unit.
In one embodiment, the LCOS back plane structure is according to the present invention include a HV CMOS transistor and a HV capacitor layer on the substrate, respectively. Herein, the HV capacitor layer can be located on the isolation structure, and the advantage of the HV capacitor layer on the isolation structure is that the area of the integrated circuit can be diminished while the capacitance achieves specific qualities. Then, an ILD (inter-layer dielectric) layer is located on the HV CMOS transistor and the HV capacitor layer. There are pluralities of contact
140
in the ILD layer which is used as a connector to electrically connect the multiple interconnect structure subsequently on the ILD layer and HV CMOS transistor and HV capacitor layer, respectively. Then, the multiple interconnect structure includes at least three metallization layer on the ILD layer. Herein, the top metallization layer of the multiple interconnect structure is a mirror layer which has highly reflective property, such that the HV CMOS transistor can generate a higher operating voltage to drive the oxide capacitor layer to increase the operating range output to the mirror layer. Furthermore, the dielectric constant of the HV capacitor layer is increased to raise the coupling ratio of the HV capacitor layer such that the HV capacitor layer can sustain the higher operating voltage to raise the capacitance operating range.
A method of forming the LCOS back plane structure according to the present invention may include forming a HV CMOS transistor and a HV capacitor layer on the substrate respectively. Then, an ILD layer is deposited on the HV CMOS transistor and HV capacitor layer. Next, a plurality of contact
140
formed in the ILD layer and a multiple interconnect structure is formed on the ILD layer by conventional interconnect technologies, and the multiple interconnect structure is electrically connected to the HV CMOS transistor and HV capacitor layer by the pluralities of contact, respectively, wherein the top metallization layer of the multiple interconnect structure is a aluminum layer that used as a mirror layer and has a highly reflective property to prevent the loss of the light scattering by a very flat surface of the mirror layer (the top metallization layer of the multiple interconnect structure), made of aluminum.
Other objects, advantages, and salient features of the invention will become apparent from the following detailed description taken in conjunction with the annexed drawings, which disclose preferred embodiments of the invention.
REFERENCES:
patent: 5566010 (1996-10-01), Ishii et al.
patent: 5867134 (1999-02-01), Alveda et al.
patent: 5966190 (1999-10-01), Dohjo et al.
patent: 6181398 (2001-01-01), Libsch et al.
Chen Ralph
Huang Ching-Chun
Tsai Yuan-Li
Yang Marcus
Yang Sheng-Hsiung
Anya Igwe U.
Merchant & Gould P.C.
Smith Matthew
United Microelectronics Corp.
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