Method of fabrication lateral FET structure having a substrate t

Details Method of fabrication lateral FET structure having a substrate t Method of fabrication lateral FET structure having a substrate t

1986-06-09

1988-04-19

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 40, 437203, 437913, 437225, 357 233, 357 234, 357 55, H01L 21302

Patent

active

047389362

ABSTRACT:
An MOS transistor is fabricated which is especially suitable for use in the VHF and UHF regions, comprising a common source lateral MOSFET formed on a substrate, the substrate serving as the connection for the source to the header. The substrate, which is preferably P-type, has P-type and N-type epitaxial regions lying thereon and a sinker which forms a connection from source to substrate. The vertically isolated field effect transistor has a drain on top of a mesa on the N-type epitaxial region of the substrate, a gate in the contact region overhanging the edge of a channel formed adjacent to the mesa, and a source in the lateral edges of the groove defining the edge of the mesa.
The process provides for simultaneous diffusion of the source and drain regions, followed by a metal masking step for connection of the diffused source which lies in the lateral edge of the groove to the sinker, effectively connecting the source to the substrate.

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