Method of fabrication a thin film SOI CMOS device

Details Method of fabrication a thin film SOI CMOS device Method of fabrication a thin film SOI CMOS device

1990-06-29

1991-01-29

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 62, 437 21, 437913, 437 34, 148150, H01L 2186, H01L 2170

Patent

active

049886380

ABSTRACT:
A thin film SOI CMOS device wherein the suitably doped deposited layers of an n-channel transistor and a p-channel transistor are simultaneously deposited. The source and drain elements of one transistor and the gate element of the other transistor are formed in a lower, highly doped, semiconductor layer and are separated from the corresponding gate element and source and drain elements formed in an upper, highly doped, semiconductor layer. The layer levels are separated by two intrinsic or lightly doped semiconductor layers sandwiching a dielectric layer, so that the intrinsic or lightly doped semiconductor layer lying contiguous to the source and drain elements serves as an active channel layer and the intrinsic or lightly doped semiconductor layer lying contiguous to the gate element serves to extend the gate layer.

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patent: 4761679 (1988-08-01), Stupp
Silicon-on-Sapphire Complementary MOS Memory Cells; Allison et al., IEEE; Dec. 67.

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