Method of fabricating wafer-level package

Details Method of fabricating wafer-level package Method of fabricating wafer-level package

1999-02-09

2000-03-28

Picardat, Kevin M.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

438109, 438118, H01L 2144

Patent

active

060431091

ABSTRACT:
A method of fabricating wafer-level package. The package is applicable in packing at least two dies. The volume of the package is approximately equal to the total volume of the packed dies. A first die is provided. A pad redistribution step is performed on the first die. After performing a pad redistribution step on the first die, an insulator is formed on a peripheral region over the first die. The insulator prevents from contaminating a central region circumscribed by the insulator over the first die during the subsequent molding or coating step. The first die is adhered onto a second die with an insulating tape or non-conductive glue. Using a bonding technique, metal wires are bonded to connect the first die and the second die, so as to transmit the signal and conduct the electricity between the first and the second dies. Using molding or coating, the metal wires are fixed and protected. Soldering balls are formed on the central region over the first die to provide terminals for connecting an external device or circuit.

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patent: 5528083 (1996-06-01), Malladi et al.
patent: 5858815 (1999-01-01), Heo et al.
patent: 5869896 (1999-02-01), Baker et al.
patent: 5879964 (1999-03-01), Paik et al.
patent: 5915169 (1999-06-01), Heo

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