Method of fabricating VLSI CMOS devices having complementary thr

Details Method of fabricating VLSI CMOS devices having complementary thr Method of fabricating VLSI CMOS devices having complementary thr

1984-03-19

1985-12-03

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29576T, 148 15, 148187, 357 67, H01L 21265, H01L 2122, H01L 2978

Patent

active

045558426

ABSTRACT:
For optimal performance, the threshold voltages V.sub.TP and V.sub.TN of the p- and n-channel transistors in a CMOS device should be the respective complements of each other. In polysilicon-gate devices, this can be achieved by adjusting the corresponding gate-metal work function utilizing p.sup.+ and n.sup.+ polysilicon for the respective gates of the p- and n-channel transistors. However, when a refractory metal silicide-over-polysilicon gate structure is employed in a VLSI CMOS device in which the gates of a pair of adjacent complementary transistors are connected together, an anomalously large negative V.sub.TP is measured.
The invention is a unique process sequence that achieves substantially complementary p- and n-channel transistor thresholds in a high-speed VLSI CMOS device that includes silicide-over-polysilicon gates.

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