Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2011-07-26
2011-07-26
Chambliss, Alonzo (Department: 2892)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S667000, C257S724000, C257S774000, C257S777000
Reexamination Certificate
active
07985620
ABSTRACT:
A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. The first set of vias are produced prior to circuitry on the die, and the second set of vias are produced after circuitry on the die. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias.
REFERENCES:
patent: 3577037 (1971-05-01), Di Pietro et al.
patent: 3648131 (1972-03-01), Stuby
patent: 4074342 (1978-02-01), Honn et al.
patent: 6400008 (2002-06-01), Farnworth
patent: 7638869 (2009-12-01), Irsigler et al.
patent: 7786008 (2010-08-01), Do et al.
patent: 2003/0111733 (2003-06-01), Pogge
patent: 2006/0121690 (2006-06-01), Pogge et al.
patent: 2008/0073752 (2008-03-01), Asai
patent: 2008/0157361 (2008-07-01), Wood et al.
patent: 2008/0258259 (2008-10-01), Osaka et al.
patent: 2010/0148371 (2010-06-01), Kaskoun
patent: 2010/0181589 (2010-07-01), Huang et al.
patent: 2133909 (2009-12-01), None
patent: 2008035261 (2008-03-01), None
patent: 2008120418 (2008-09-01), None
International Search Report—PCT/ US2009/067682, International Search Authority—European Patent Office May 11, 2010.
Written Opinion—PCT/ US2009/067682, International Search Authority—European Patent Office May 11, 2010.
Kommera S et al: “Novel through-die connections for MEMS applications” XP9022355, Database accession No. 7764513, Database Inspec [Online], The Institution of Electrical Engineers, Stevenage, GB; 2003, & Micromachining and Microfabrication Process Technology VII Jan. 27-29, 2003 San Jose, CA, USA, vol. 4979, 2003, pp. 261-270, Proceedings of the SPIE—The International Society for Optical Engineering SPIE—Int. Soc. Opt. Eng USA, LNKD—doi:10.1117/12.472804, ISSN: 0277-786X.
Gu Shiqun
Kaskoun Kenneth
Swinnen Bart
Chambliss Alonzo
Gallardo Michelle S.
Qualcomm Incorporated
LandOfFree
Method of fabricating via first plus via last IC interconnect does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating via first plus via last IC interconnect, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating via first plus via last IC interconnect will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2706086