Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
1999-04-12
2002-04-16
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S202000
Reexamination Certificate
active
06373122
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the manufacture of integrated circuit (IC) chips, and more particularly to a method of forming a plurality of passivated IC chips of various sizes, with guard rings and input-output (I/O) pads, from a borderless gate array wafer.
BACKGROUND OF THE INVENTION
IC chips are the heart of practically all modern electronic devices. They are typically manufactured by forming one or more arrays of unconnected gates or transistors on a silicon wafer, and then metalizing the array through masks to form interconnections between gates, and between gates and connection pads, that gives a chip its individuality and functionality.
Wafers are typically available in two types: standard-size arrays and borderless arrays. In the standard-size type, a set of individual arrays of a standard size are formed on each wafer, together with surrounding I/O pads and appropriate passivation structures for chemical isolation against environmental contaminants, as well as guard rings for electrical isolation against stray electromagnetic interference. After the interconnections have been formed, the wafer is cut between the arrays to provide individual finished chips.
In the borderless array type of wafer, a single array is formed to cover the entire surface of the wafer. Individual ICs are produced, after the formation of interconnections, by cutting through unused portions of the array. This method does not, however, lend itself to passivation.
Masks for the production of wafers and the formation of interconnections are extremely expensive, so that the manufacture of custom wafers is not economically practical for the production of chips in quantities less than hundreds of thousands. Yet there are many instances in which only a few thousand chips of any particular design are required. In order to economically produce such quantities, a wafer must be able to carry a large number of IC arrays of varying sizes for different purposes and/or different customers. This allows many different IC chips to be produced simultaneously with a single mask.
Problems arise in carrying out the latter method with either of the traditional types of wafers. In a standard-size array wafer, the array size must be large enough to accommodate the largest IC to be produced on the wafer. Consequently, substantial portions of the array are wasted for smaller ICs. Borderless arrays can be cut as desired to fit various-sized ICs on a wafer without substantial waste; however, borderless arrays, which are uniform throughout the wafer surface, do not lend themselves to passivation. Passivation structures can only be formed where the wafer substrate is accessible, i.e. where no transistor array has been formed on the wafer.
It is therefore desirable to provide a fabrication method which allows many ICs of varying sizes to be formed on a uniform generic wafer, yet allows passivation structures and guard rings to be formed around each individual IC regardless of its size or shape.
SUMMARY OF THE INVENTION
The invention overcomes the deficiencies of the prior art by forming on the surface of the wafer a borderless array composed of micro arrays or blocks about 200×200 &mgr;m in size, separated by about 10 &mgr;m wide strips in which the substrate is exposed. ICs are formed by metalizing sets of blocks which together have the requisite size and shape for the desired IC. The strips consume about 10% of the wafer surface, but the exposure of the substrate in the strips makes it possible to form passivation structures and (by forming areas of p
+
and/or n
+
diffusion in the strip) guard rings around any selected set of blocks. The 10 &mgr;m gap between blocks is not sufficient to interfere with the transmission of signals between gates in adjacent blocks.
In an additional aspect of the invention, unused blocks or portions of blocks within the layout of a particular IC may be metalized to form input/output connection pads. The versatility of the wafer can be improved by providing alternate rows or columns with various types of application-specific gate elements, such as transistors designed for use in analog or digital circuits; mixtures of transistors and resistors; or combinations of these.
In still another aspect of the invention, a variety of different layers and/or circuits can be metalized with a single mask by arranging all necessary patterns on the mask, and then covering all except the desired pattern during exposure.
REFERENCES:
patent: 4688072 (1987-08-01), Heath et al.
patent: 4775942 (1988-10-01), Ferreri et al.
patent: 4978633 (1990-12-01), Seefeldt et al.
patent: 5459340 (1995-10-01), Anderson et al.
patent: 5629552 (1997-05-01), Zommer
patent: 5656833 (1997-08-01), Kajihara
patent: 5721151 (1998-02-01), Padmanabhan et al.
patent: 5976392 (1999-11-01), Chen
Luo Jin
Sivilotti Massimo Antonio
Tanner John Edward
Crane Sara
Stout, Uxu, Buyan & Mullins, LLP
Tanner Research, Inc.
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