Method of fabricating up diffused substrate FED logic utilizing

Details Method of fabricating up diffused substrate FED logic utilizing Method of fabricating up diffused substrate FED logic utilizing

1978-06-27

1980-12-23

Rutledge, L. Dewayne

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

29576W, 29577R, 148187, 148191, 357 44, 357 46, 357 89, 357 90, 357 92, H01L 2120, H01L 2702

Patent

active

042408466

ABSTRACT:
A complementary pair of vertically aligned, inversely operated transistors formed from a P type substrate, a first N type epitaxial layer, a second N type epitaxial layer and a buried, updiffused P type region between the two epitaxial layers. The impurity concentration of the buried region decreases from its junction with the first epitaxial layer to its junction with the second epitaxial layer whose impurity concentration is less than that of the first epitaxial layer. High impurity concentration N type guard ring and P type base ring are diffused simultaneously with the out diffusion of the buried P type region into the second epitaxial layer. The substrate, first epitaxial layer and buried region constitute the emitter, base, and collector of the inverse vertical PNP transistor and the first epitaxial layer, buried region and second epitaxial layer constitute the emitter, base, and collector of the inverse vertical NPN transistor.

REFERENCES:
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patent: 4051506 (1977-09-01), Horie
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patent: 4106049 (1978-08-01), Shinozaki et al.
patent: 4140559 (1979-02-01), Van Vonno
McGreivy, et al., "Up-Diffused I.sup.2 L . . . Process", Tech. Digest Int'l. Electron Devices MTG, Wash., D. C., Dec., 1976, pp. 308-311.
Stone, J. L., "I.sup.2 L:A Comprehensive Review . . . of Technology", Solid State Technology, Jun., 1977, pp. 42-48.

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