Method of fabricating topside structure of a semiconductor devic

Details Method of fabricating topside structure of a semiconductor devic Method of fabricating topside structure of a semiconductor devic

1997-09-04

1999-11-23

Niebling, John F.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Having light transmissive window

438791, 438 64, H01L 2144, H01L 2148, H01L 2100, H01L 2131

Patent

active

059899387

ABSTRACT:
The present method and apparatus provides a thin layer of oxynitride over a device including a patterned metal layer, application of a planarizing SOG layer over the thin oxynitride layer, removal of thin portions of the SOG layer by etching to expose portions of the thin oxynitride layer, and application of a thick oxynitride layer to form a strong bond with the thin oxynitride layer. A thin nitride layer, transparent to UV light, may then be applied to the resulting structure prior to application of plastic packaging material.

REFERENCES:
patent: 4618541 (1986-10-01), Forouhi et al.
patent: 4775550 (1988-10-01), Chu et al.
patent: 4965226 (1990-10-01), Gootzen et al.
patent: 5217926 (1993-06-01), Langley
patent: 5527872 (1996-06-01), Allman
Wolf, S.; Silicon Processing for the VLSI Era, vol. 2; Lattice Press, Sunset Beach, Ca.; pp. 273-276, 1990.

Affiliated with

Also associated with

Rating

Method of fabricating topside structure of a semiconductor devic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating topside structure of a semiconductor devic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating topside structure of a semiconductor devic will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1221000