Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
1998-12-15
2001-05-08
Niebling, John F. (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S382000, C338S225000
Reexamination Certificate
active
06228735
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a thin film resistor of an interconnect by dual damascene.
2. Description of the Related Art
Dual damascene is a technique which fabricates planar and vertical interconnects at the same time. An insulation layer is formed on a substrate. After planarization, the pattern of conductive wires and contact window is transferred. The insulation layer is then etched to form a trench for the planar interconnects, and a contact window for vertical interconnects. A metal layer is formed to fill the trench and the contact window to form the conductive wires and the contact at the same time. The interconnection is thus achieved. Silicon has a certain solid solubility for metal at a high temperature. While a high temperature process is performed, a mutual diffusion occurs between silicon atoms and metal atoms to cause spikings. The spikings are often too long to cause a short circuit by piercing through the silicon. The short circuit affects the performance of devices greatly, and sometimes even causes a device failure. Therefore, a barrier layer is formed between a metal layer and a silicon layer to avoid the spiking effect, as well as to enhance the adhesion between silicon and metal.
A resistor is a component commonly used in both memory and logic circuit. The resistance of a resistor is a function of both the length and cross sectional surface area, that is, R=&rgr;
L/A
, wherein, &rgr; is the resistivity, L is the length through which current flowing, and A is the cross sectional surface area which current flowing through.
A resistor in an integrated circuit is typically formed by lightly doping a polysilicon region. Strips of polysilicon with various length and cross sections are formed as resistors with different resistance. Alternatively, resistors with various different resistance may also be formed by high resistant conductor and low resistant conductor. Typically, the low resistant conductor is formed by doped polysilicon, while the high resistant conductor is formed undoped polysilicon. As the integration of a semiconductor device is increased, the quality demand of material for forming the semiconductor device is raised. For example, to obtain a device with a reduced surface or volume, a resistor with a sufficiently high resistance has to be formed with a restricted dimension. However, the resistance per unit area and length of material such as polysilicon is limited, and thus, causes the difficulty for the fabrication of device with a high integration.
To increase the resistance per unit of a resistor, material such as chromium silicide (Cr
x
Si
y
) has been used to fabricate resistant layer to replace the doped or undoped polysilicon.
FIG. 1A
to
FIG. 1C
shows a fabrication method for forming a thin film resistor.
In
FIG. 1A
, a substrate
100
is provided. A borophosphosilicate glass (BPSG) layer
102
is formed on the substrate
100
. A thin film resistant layer
104
is formed on the BPSG layer
102
. Using sputtering, a metal layer made of aluminum or alloy of aluminum/silicon/copper (Al/Si/Cu)
106
is formed on the BPSG layer
104
to protect the thin film resistant layer
104
from being etched in a subsequent dry etching process.
In
FIG. 1B
, the metal layer
106
is patterned, and the remaining metal layer
106
a
is formed as an etching mask for defining the underlying thin film resistant layer
104
. The defined thin film resistant layer is denoted as
104
a
. The BPSG layer
102
is defined by dry etching to form a contact window
110
penetrating through the resultant BPSG layer
102
a
. A conductive layer
112
is formed over the substrate
100
and to fill the contact window
110
.
In
FIG. 1C
, the conductive layer
112
is patterned as a conductive layer
11
2
a
of a conductive wire for interconnection
112
a
. The metal layer
106
a
is stripped to expose the thin film resistant layer
104
a
. After the formation of the thin film resistant layer
104
a
, an electric characteristic test is typically performed. A laser cutting machine is often used to cut the thin film resistant
104
a
into a thin film resistor with a required resistance. Therefore, the requirement of the circuit design can be more precisely achieved.
However, in the conventional method, an aluminum contained metal layer
106
is formed as a protection layer as the thin film resistant layer
104
a
. While a barrier layer is formed by material containing titanium, the aluminum in the protection layer will react with titanium. As a consequence, the protection layer cannot effectively protect the thin film resistant layer
104
a
. A conformal barrier for improving the adhesion between a contact window and a contact plug and to avoid the spike effect can not be formed in the contact window.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a protection layer to protect a thin film resistant layer. In addition, the protection layer is not affected or damaged by the formation of a barrier layer.
To achieve the above-mentioned objects and advantages, a method of fabricating a thin film resistor is provided. A substrate having an insulating layer thereon is provided. The thin film resistor is formed to cover a part of the insulating layer. An oxide layer is formed on the thin film resistant layer and the insulation layer. The oxide layer and the insulating layer are patterned to form a contact window to expose a part of the substrate. A conformal barrier layer is formed to cover the oxide layer and the contact window surface. A part of the barrier layer and a part of the oxide layer are removed to expose the thin film resistor and a part of the insulating layer. A contact is formed to fill the contact window and a conductive pattern is formed on a part of the thin film resistor.
In the invention, a thin oxide layer is formed as a protection layer to protect the thin film resistor from being etched by ions during the subsequent dry etching process. Furthermore, a barrier layer is formed to enhance the adhesion between the contact and the contact window, so as to prevent the spiking effect without damaging the protecting layer.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 4682402 (1987-07-01), Yamaguchi
patent: 4725810 (1988-02-01), Foroni et al.
patent: 5030588 (1991-07-01), Hosaka
patent: 6090678 (2000-07-01), Maghsoudnia
patent: 6140198 (2000-10-01), Liou
patent: B1 6180479 (2001-01-01), Yoshikawa
Niebling John F.
Simkovic Viktor
Thomas Kayden Horstemeyer & Risley
United Microelectronics Corp.
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