Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support
Reexamination Certificate
2008-07-29
2008-07-29
Chambliss, Alonzo (Department: 2892)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Insulative housing or support
C438S612000, C257S773000, C257S784000, C257SE23145
Reexamination Certificate
active
11011442
ABSTRACT:
A method for manufacturing a layered structure for routing electrical signals comprising the steps of providing a layout for the layered structure having an insulating layer with at least one signal trace, a via, and a stub trace on a first side of the insulating layer, and a generally planar electrically conductive layer disposed on a second side of the insulating layer. Identify the stub trace and define a beneficial portion on the second side based upon a layout of the stub trace where the electrically conductive layer on the second side is to be absent. Modify the layout according to the step of defining and manufacture the layered structure according to the modified layout.
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Avago Technologies General IP Pte Ltd
Chambliss Alonzo
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