Method of fabricating the routing of electrical signals

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support

Reexamination Certificate

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C438S612000, C257S773000, C257S784000, C257SE23145

Reexamination Certificate

active

11011442

ABSTRACT:
A method for manufacturing a layered structure for routing electrical signals comprising the steps of providing a layout for the layered structure having an insulating layer with at least one signal trace, a via, and a stub trace on a first side of the insulating layer, and a generally planar electrically conductive layer disposed on a second side of the insulating layer. Identify the stub trace and define a beneficial portion on the second side based upon a layout of the stub trace where the electrically conductive layer on the second side is to be absent. Modify the layout according to the step of defining and manufacture the layered structure according to the modified layout.

REFERENCES:
patent: 5576519 (1996-11-01), Swamy
patent: 6163957 (2000-12-01), Jiang et al.
patent: 6275358 (2001-08-01), Balakrishnan et al.
patent: 6521845 (2003-02-01), Barrow
patent: 6632343 (2003-10-01), Farnworth et al.
patent: 6740978 (2004-05-01), Huang et al.
patent: 6800944 (2004-10-01), Buschbom

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