Semiconductor device manufacturing: process – Forming schottky junction – Compound semiconductor
Reexamination Certificate
2001-10-03
2003-03-11
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Forming schottky junction
Compound semiconductor
C438S300000, C438S592000, C438S291000
Reexamination Certificate
active
06531380
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to formation of semiconductor devices, and more specifically the formation of T-shaped polysilicon gates used in semiconductor devices.
BACKGROUND OF THE INVENTION
The requirement of increasingly small design rule for complementary metal-oxide semiconductor (CMOS) processes conflict with the requirements of salicide (self-aligned silicide) processes because very shallow junctions lead to junction leakage. On the other hand, the salicide sheet resistance (rho) of the polysilicon gate increases quickly when the width of the polysilicon gate scales down to the deep submicron range, e.g. 0.25 &mgr;m. The higher salicide sheet rho of the polysilicon gate reduces circuit speed.
U.S. Pat. No. 5,817,558 to Wu describes a semiconductor processing method for forming self-aligned T-gate lightly-doped drain (LDD) device having a recessed channel. An oxide layer is formed over a substrate followed by forming a nitride layer over the oxide layer. The nitride and oxide layers are etched to expose the underlying substrate and to define a gate region. Polysilicon spacers are formed of the side walls of the nitride layer then an anisotropic etch is used to etch the sidewall spacers and the exposed substrate to form a T-shaped groove. Amorphous silicon is deposited, filling the T-shaped groove then the excess amorphous silicon and the nitride layer is removed to form a T-gate.
U.S. Pat. No. 5,621,233 to Sharma et al. describes electrically programmable read-only memory cells having T-shaped floating gates and control gates that surround almost all of the T-shaped floating gates except those that lie on a gate dielectric layer.
U.S. Pat. No. 5,940,697 to Yoo et al. a method for forming a T-gate structure in a metal-semiconductor field effect transistor (MESFET) that includes dielectric lift-off steps.
U.S. Pat. No. 5,559,049 to Cho describes a method of manufacturing a semiconductor device having a T-shaped gate electrode. Auxiliary gates are capacitively coupled with the T-shaped gate at undercut portions below both sides of the T-shaped gate.
U.S. Pat. No. 5,688,704 to Liu describes a method of fabricating an integrated circuit having a T-shaped polysilicon gate that facilitates the formation of rectangular-shaped silicon nitride spacers.
U.S. Pat. No. 5,783,479 to Lin et al. describes a structure and method for fabricating field effect transistors (FETs) having T-shaped gates that can reduce the parasitic resistance of the gate and source/drain.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of forming a T-shaped recessed gate conductor for a semiconductor device that increases the surface area of the polysilicon gate and reduces the silicide sheet resistance (rho) of the polysilicon gate.
Another object of the present invention is to provide a method of forming a T-shaped recessed gate conductor for a semiconductor device that resolves the conflict with a shallow junction and a silicide process by not requiring too shallow a junction and thus minimizes junction leakage.
A further object of the present invention is to provide a method of forming a T-shaped recessed gate conductor for a semiconductor device such that the recessed gate conductor makes it easy to control the efficient gate length by accurately controlling the source/drain implantation energy.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure is provided having an upper silicon layer, a pad dielectric layer over the upper silicon layer, and a well implant within a well region in the upper silicon layer. A lower SiN layer is deposited and patterned over the pad dielectric layer to define a lower gate area. The pad dielectric layer and the upper silicon layer within the lower gate area is etched to form a lower gate trench having a predetermined width. A lower gate portion is formed within the lower gate trench. An upper oxide layer is formed over the lower SiN layer. An upper SiN layer is formed over the upper oxide layer. The upper SiN layer is etched to define an upper gate trench having a predetermined width greater than the lower gate trench predetermined width. An upper gate portion is formed within the upper gate trench, wherein the lower and upper gate portions form a T-shaped gate. The etched upper SiN, upper oxide, and lower SiN layers are removed to expose the T-shaped gate extending above the pad dielectric layer. An uppermost oxide layer is formed over the exposed T-shaped gate. SiN sidewall spacers are formed adjacent the exposed vertical side walls of the lower polysilicon gate portion. Silicide regions are formed over the T-shaped gate and source/drain regions.
REFERENCES:
patent: 5559049 (1996-09-01), Cho
patent: 5621233 (1997-04-01), Sharma et al.
patent: 5688704 (1997-11-01), Liu
patent: 5783479 (1998-07-01), Lin et al.
patent: 5817558 (1998-10-01), Wu
patent: 5940697 (1999-08-01), Yoo et al.
patent: 6303448 (2001-10-01), Chang et al.
Gan Chock Hing
Li Xia
Chartered Semiconductor Manufacturing Ltd.
Le Dung
Nelms David
Pike Rosemary L. S.
Saile George O.
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