Fishing – trapping – and vermin destroying
Patent
1993-06-03
1994-12-27
Fourson, George
Fishing, trapping, and vermin destroying
437924, 437 8, 148DIG28, H01L 21302
Patent
active
053765893
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to similar semiconductor chips, which are produced together on a plate and subsequently dissociated.
BACKGROUND INFORMATION
As is well known, nowadays semiconductor components or chips are efficiently produced on discoid plates, called wafers, which are sliced off of bar-shaped silicon monocrystals. Various technologies, such as photolithography, epitaxy, diffusion, masking methods and the like are used to form a plurality of similar integrated circuits on such a plate. After being separated into single chip crystals, they can no longer be differentiated from one another. If clusters of defects in the circuits occur later, it can no longer be determined afterwards whether these are statistically distributed defects or if they are defects that have accumulated in certain regions of the plates. It would be quite advantageous if, in searching for the cause of the defects, one were still able to discover later on the original position of the particular chip on the plate.
SUMMARY OF THE INVENTION
The present invention provides a method of producing first and second semiconductor chips from a plate of monocrystalline semiconductor material. First and second monolithically integrated circuits are formed on the plate. An identifying plate position marking is then provided on the edge area between the first and second circuits. The first and second circuits are dissociated to form the first and second chips, respectively. The width of the edge area is selected and the marking on the edge area is arranged such that the marking is retained on at least one of the first and second chips after the dissocation.
The advantage of the solution according to the present invention, is that even after the dissociation, the earlier position of the individual chips can be read off from the plate. One can then correlate the individual fates of the chips with their earlier position on the plate. Since these identifying markings can be applied together with the semiconductor structures of the chips during the manufacturing process, there is only a marginal increase in production expenditure. One merely needs to modify the photomask, for example, which can then be used to index all similar components during the planar process in a simple and especially robust manner.
The measures specified in the dependent claims make it possible to advantageously further develop and improve the semiconductor chips indicated in claim 1.
It proves to be particularly advantageous to configure the identifying markings on edge areas situated between the semiconductor structures (layouts) of adjacent semiconductor chips. One can thus avoid any kind of circuit-engineering interventions or controls, and ample space is available on the edge areas for the identifying markings. Another advantage is the ease with which the identifying markings can be read off from these edge areas. Already existing components can also be indexed with such identifying markings, without the necessity of having to change the layouts. The edge area between two chips, the so-called slicing trough, cannot be used anyway up to a certain width for layout components. This is because when the plate is sawn apart, on the one hand, a strip is sawn away and, on the other hand, slicing tolerances must be taken into consideration, whereby because of the adjusting tolerance, the position of the slicing trace within the slicing trough cannot be exactly determined beforehand.
The identifying markings allocated to the adjacent semiconductor chips are expediently offset toward the respective allocated semiconductor chip on the edge areas, which are situated in-between and are wider than the identifying markings. As a result, it is possible for the remaining identifying markings to be perfectly allocated to the particular chip independently of the adjusting tolerance of the slicing trace. The width of the identifying markings can be dimensioned, thereby, so that given an optimum middle cut, each chip, after being dissociated, still bears o
REFERENCES:
patent: 3562536 (1971-02-01), Brunner et al.
patent: 4134066 (1979-01-01), Vogel et al.
patent: 4981529 (1991-01-01), Tsujita
IBM Technical Disclosure Bulletin, vol. 14, No. 4, Sep. 1971, New York, pp. 1030-1031, R. C. Fahrni, et al, "Wafer Identification".
Fourson George
Mason David M.
Robert & Bosch GmbH
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