Method of fabricating silicon-on-insulator transistors with a sh

Details Method of fabricating silicon-on-insulator transistors with a sh Method of fabricating silicon-on-insulator transistors with a sh

1984-06-28

1987-03-17

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29576E, 29580, 148DIG164, 148DIG150, 148DIG135, H01L 2978

Patent

active

046496270

ABSTRACT:
A method of fabricating a shared element semiconductor structure in which the insulating layer of a silicon-on-insulator structure is patterned to form a gate oxide. The bulk semiconductor underlying the insulating layer is defined into an FET (field-effect transistor) with its gate region below the gate oxide. The epitaxial layer above the insulating layer is defined into another FET with its drain region above the gate oxide, whereby the drain region also operates as the gate electrode for the bulk FET. Also described is a method of forming a silicon on insulator substrate with insulating layer usable as a gate oxide by means of bonding a silicon substrate to an oxidized epitaxial layer on another silicon seed substrate and then removing the seed substrate.

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Kimura et al., "Epitaxial Jem Transfer Technique" Appl. Phys. Lett 43(3), Aug. 1, 1983, pp. 263-265.
Lam, "Silicon on Insulating Substrates" Internatn. Electron Devices Meeting, Dec. 1983, pp. 348-351.
Jastrzebski, "Comparison of Different SOI Tech", RCA Review, vol. 44, Jun. 1983, pp. 251-269.
Douglas, "The Route to 3-D Drops", High Technology, Sep. 1, 1983, pp. 55-59.

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