Method of fabricating silicon-on-insulator like devices

Details Method of fabricating silicon-on-insulator like devices Method of fabricating silicon-on-insulator like devices

1986-12-10

1987-12-29

Ozaki, George T.

Fishing, trapping, and vermin destroying

437200, H01L 21365, H01L 41425

Patent

active

047161280

ABSTRACT:
A process for forming MOS transistors in which the source and drain regions essentially interface only the channel portion of the silicon substrate to keep parasitic capacitances low. To this end, a monocrystalline silicon substrate has one major planar surface covered with a layer of silicon oxide and a hole formed in the oxide layer of a size suited for the channel of the transistor. Then silicon is epitaxially grown vertically to fill the hole. The grown silicon is then covered. Next, portions of the oxide layer are removed to expose a pair of opposed vertical sidewalls of the vertically grown silicon and silicon is epitaxially grown laterally out of said exposed sidewalls. Such laterally grown regions serve as the source and drain of the transistor and an upper portion of the vertically grown silicon serves as the channel. A gate oxide is grown over a top portion of the vertically grown silicon and a polysilicon gate region is formed over the gate oxide. The gate region then serves as a mask which allows the laterally grown drain and source regions to be doped and to be self-aligned to the gate region.

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