Method of fabricating short-gate-length electrodes for...

Details Method of fabricating short-gate-length electrodes for... Method of fabricating short-gate-length electrodes for...

2008-05-15

2010-11-30

Vu, Hung (Department: 2811)

Semiconductor device manufacturing: process

Forming schottky junction

Compound semiconductor

C438S182000, C438S574000, C438S949000, C438S950000, C257S183100, C257S194000, C257S197000, C257SE21205, C257SE29189

Reexamination Certificate

active

07842591

ABSTRACT:
A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity.

REFERENCES:
patent: 5288660 (1994-02-01), Hua et al.
patent: 6078067 (2000-06-01), Oikawa
patent: 2003/0116782 (2003-06-01), Mizutani
patent: 2005/0184310 (2005-08-01), Krutko et al.
patent: 2006/0102932 (2006-05-01), Hwang

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