Method of fabricating shallow trench isolation structure

Details Method of fabricating shallow trench isolation structure Method of fabricating shallow trench isolation structure

1998-12-08

2001-02-20

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

C438S424000, C438S425000

Reexamination Certificate

active

06190995

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of fabricating a shallow trench isolation (STI) structure, and more particularly to a method of fabricating a shallow trench isolation structure that can prevent micro-scratches from occurring on the STI structure.
2. Description of the Related Art
STI structure is widely used in semiconductor process of 0.25 &mgr;m. The fabrication of the STI structure includes the step of anisotropically etching a trench within a substrate, depositing an oxide layer in the trench and planarizing the oxide layer by chemical mechanical polishing (CMP) to provide an even surface.
FIGS. 1A-1F
are side views illustrating fabrication of a STI structure in prior art. Referring to
FIG. 1A
, a pad oxide layer
11
is thermally formed on a substrate
10
. A silicon nitride layer
12
is formed on the pad oxide layer
11
by chemical vapor deposition (CVD).
Referring to
FIG. 1B
, a patterned photoresist layer
13
is formed on the silicon nitride layer
12
. Using the photoresist layer
13
as an etching mask, a portion of the silicon nitride layer
12
, the pad oxide layer
11
and the substrate
10
are removed to form a trench
16
within the substrate
10
.
Referring to
FIG. 1C
, the photoresist layer
13
of
FIG. 1B
is removed. A liner oxide layer
14
is formed on the sidewall of the trench
16
.
Referring to
FIG. 1D
, a silicon oxide layer
15
is formed on the liner oxide layer
14
and the silicon nitride layer
12
to fill the trench
16
.
Referring to
FIG. 1E
, a portion of the silicon oxide layer
15
is removed by CMP to expose the silicon nitride layer
12
.
Referring to
FIG. 1F
, the silicon nitride layer
12
and the pad oxide layer
11
are removed, respectively, by wet etching and the STI structure is completed.
The silicon nitride layer
12
is used as a stop layer and CMP is performed on the silicon oxide layer
15
in the process as described above. During the process of CMP, since the hard material of the silicon nitride layer
12
is polished by CMP, silicon nitride particles are easily produced from polishing and cause micro-scratch
17
to occur on the silicon oxide layer
15
a.
Stringer is thus produced on a polysilicon layer subsequently deposited and a short occurs in the semiconductor device. Otherwise, the in the foregoing process, it is necessary to remove the silicon nitride layer
12
by dry etching, which increases both the cost of the fabrication and cycle time of the process. In addition, stress between the silicon nitride layer
12
, the pad oxide layer
11
and the silicon oxide layer
15
a
causes dislocation of surface atoms of the substrate
10
and reduces the reliability of devices.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of fabricating a STI structure to prevent micro-scratches from occurring on the STI structure.
It is another object of the invention to provide a method of fabricating a STI structure to prevent dislocation from happening in the substrate.
It is yet another object of the invention to provide a method of fabricating an STI structure with a simplified process and reduced process cycle time of the process can be reduced.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of fabricating a shallow trench isolation structure. A silicon oxide layer is formed on a substrate. The silicon oxide layer is patterned and a portion of the substrate is removed to form a trench within the substrate. A liner oxide layer is formed on the sidewall of the trench. An insulating layer is formed on the substrate and fills the trench. A portion of the insulating layer is removed by CMP to expose the silicon oxide layer. The silicon oxide layer is removed and the STI structure is completed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5918131 (1999-06-01), Hsu et al.
patent: 5981353 (1999-11-01), Tsai
patent: 5981402 (1999-11-01), Hsiao et al.
patent: 5994201 (1999-11-01), Lee
patent: 6037237 (2000-03-01), Park et al.
“Silicon Processing For VSLI Era” Wolf et al. pp. 182-189, Jan. 1986.

Affiliated with

Also associated with

Rating

Method of fabricating shallow trench isolation structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating shallow trench isolation structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating shallow trench isolation structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2603915