Method of fabricating shallow trench isolation structure

Details Method of fabricating shallow trench isolation structure Method of fabricating shallow trench isolation structure

1999-03-29

2001-05-01

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S778000

Reexamination Certificate

active

06225189

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88103454, filed Mar. 6, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating an isolation region.
2. Description of the Related Art
An isolation region is formed in an integrated circuit for the purpose of separating neighboring device regions of a substrate and preventing the carriers from penetrating through the substrate to neighboring devices. For example, isolation regions are used to isolate field effect transistors (FETs) from each other in order to prevent current leakage among the FETs. Conventionally, local oxidation of silicon (LOCOS) technique is widely utilized in semiconductor industry to provide the isolation regions among the various devices in the substrate. However, there are still some drawbacks, such as internal stress generation and bird's beak encroachment, in the LOCOS process. Shallow trench isolation (STI) has become widely used in highly integrated devices because STI is scaleable and has no bird's beak encroachment problem as found in the conventional LOCOS technique.
In the fabrication process of the STI structure, an isolation layer is deposited to fill the trench and then a chemical-mechanical polishing step is performed in order to obtain a planarized surface. However, because self-planarization of the isolation layer is poor, it is easy to obtain surface having a deep step height after chemical-mechanical polishing.
In the conventional method of forming the shallow trench isolation, the surface having a deep step height over the substrate causes dishing in the isolation layer. Because electrons easily gather in the recessed isolation layer, which is arising from dishing, the threshold voltage of devices is decreased and the abnormal sub-threshold current is likely to occur. The aforementioned problem is called a kink effect, which degrades the device quality and decreases the throughput.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a shallow trench isolation (STI) structure. A mask layer is formed on a substrate. The mask layer and the substrate are patterned to form a trench in the substrate. A first deposition step and a second deposition step are performed to form a first isolation layer over the substrate. A third deposition step is performed to form a second isolation layer on the first isolation layer. A planarization process is performed with the mask layer serving as a stop layer. A portion of the first isolation layer and the mask layer are removed to form the STI structure.
The fluidity of the second isolation layer is greater than the fluidity of the second isolation layer. Thus, the second isolation layer has a good gap-filling ability. A planarized surface over the substrate is obtained after the second isolation layer is formed. A highly planarized surface can be further obtained after the following chemical-mechanical polishing. Additionally, in the present invention, neither the kink effect nor the abnormal sub-threshold current occur.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5051380 (1991-09-01), Maeda et al.
patent: 5786262 (1998-07-01), Jang et al.
patent: 5817567 (1998-10-01), Jang et al.
patent: 5891810 (1999-04-01), Park et al.

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