Method of fabricating shallow trench isolation

Details Method of fabricating shallow trench isolation Method of fabricating shallow trench isolation

1999-01-25

2001-05-29

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

C438S424000

Reexamination Certificate

active

06238997

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of forming an isolation region in the substrate.
2. Description of the Related Art
Shallow trench isolations (STIs) are formed in an integrated circuit for the purpose of separating neighboring device regions of a substrate and preventing the carriers from penetrating through the substrate to neighboring devices. A shallow trench isolation is formed by first using anisotropic etching to form a trench in the substrate, and then depositing oxide in the trench to form an isolation region. The shallow trench isolations are commonly used to separate neighboring MOS devices.
FIGS. 1A through 1D
are schematic, cross-sectional views showing a conventional method of fabricating a shallow trench isolation.
In
FIG. 1A
, a pad oxide layer
107
is formed on a semiconductor substrate
105
. A silicon nitride layer
111
is formed on the pad oxide layer
107
by chemical vapor deposition (CVD). A patterned photoresist layer (not shown) is formed on the silicon nitride layer
111
. An etching process is performed by using the photoresist layer as a mask. The silicon nitride layer
111
, the pad oxide layer
107
, and the semiconductor substrate
105
are patterned. A trench
112
is formed in the semiconductor substrate
105
to define active regions
109
of the substrate
105
. The photoresist layer is removed.
In
FIG. 1B
, a silicon oxide layer
113
is formed by chemical vapor deposition to fill the trench
112
.
In
FIG. 1C
, a photoresist layer is formed on the silicon oxide layer
113
. The photoresist layer is patterned. The patterned photoresist layer is used as a mask for a reverse patterning process. In the reverse patterning process, an anisotropic etching step is performed. The silicon oxide layer
113
on the active regions
109
are removed by a reverse patterning process to form a silicon oxide layer
113
a
as shown in
FIGS. 1B and 1C
. The photoresist layer is removed to expose the silicon oxide layer
113
a.
A chemical-mechanical polishing process is performed to polish the silicon oxide layer
113
a
until a thickness of about 50 nm remains above the silicon nitride layer
111
in order to prevent the occurrence of micro-scratches on the substrate
105
. Finally, as seen in FIG
1
D, the silicon nitride layer
111
, the pad oxide layer
107
and a portion of the silicon oxide layer
113
a
are removed by wet etching. A shallow trench isolation
115
having a smooth surface that is level with the substrate
105
is formed.
However, it is difficult to obtain a uniform film in thickness after the anisotropic etching step because of the original topography, and thus the remaining thickness of the silicon oxide layer
113
a
on the silicon nitride layer
111
of each active region
119
varies after anisotropic etching. This, in turn, affects the performance of the following chemical-mechanical polishing and makes it difficult to obtain a uniform remaining silicon oxide layer
113
a
on the silicon nitride layer
111
. So, in practice, the uniform thickness of 50 nm on the silicon nitride layer
111
is rarely achieved. The continuing lack of a uniform surface affects the wet etching process, which results in a shallow trench isolation
115
whose surface is not flat or level with the substrate
105
surface.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a shallow trench isolation. A pad oxide layer, a mask layer, a first oxide layer, and a polysilicon layer are formed in sequence over a substrate. The polysilicon layer, the first oxide layer, the mask layer, the pad oxide layer, and the substrate are patterned to form a trench exposing a portion of the substrate. A second oxide layer is formed on the polysilicon layer to fill the trench. A portion of the second oxide layer on the polysilicon layer is removed to expose the polysilicon layer. The second oxide layer, the polysilicon layer, and a portion of the first oxide layer are removed. A portion of the second oxide layer, the first oxide layer, the mask layer, and the pad oxide layer are removed to obtain a smooth surface over the substrate.
One aspect of the invention involves substitution of a thin poly silicon layer for the polysilicon layer. A preserve layer is further formed on the thin polysilicon layer. The preserve layer is used to protect the thin polysilicon layer in order to prevent it from being oxidized. Additionally, the preserve layer and the second oxide layer can be removed simultaneously to expose the thin polysilicon layer in the etching process.
The invention provides the polysilicon layer formed below the oxide layer. The polysilicon layer provides a good etching stop while the oxide layer is etched. In this manner, the shallow trench isolation is formed with a flat surface, which is level with the substrate surface. In addition, the present invention prevents the occurrence of microscratches formed in the surface of the shallow trench isolation.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5904538 (1999-05-01), Son et al.
patent: 5981357 (1999-11-01), Hause et al.
patent: 6037237 (2000-03-01), Park et al.
patent: 6069091 (2000-05-01), Chang et al.
patent: 6093618 (2000-07-01), Chen et al.

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