Method of fabricating shallow trench isolation

Details Method of fabricating shallow trench isolation Method of fabricating shallow trench isolation

1998-06-24

2000-08-29

Bowers, Charles

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438400, 438438, 438435, 438238, 257647, H01L 2176

Patent

active

061107956

ABSTRACT:
An method of fabricating a shallow trench isolation. A semiconductor substrate having pad oxide layer and a hard mask layer is provided. The pad oxide layer and the hard mask layer are defined to expose a part of the substrate. The exposed substrate is etched to form a trench therewithin. An isolation layer is formed to fill the trench. The isolation layer is planarized by chemical mechanical polishing with the hard mask layer as an stop layer, so that a micro-scratch is formed on a surface of the isolation within the trench. A sacrificial layer is formed on the isolation layer and the hard mask layer. The micro-scratch is thus filled with the sacrificial layer. Using the hard mask as an etch stop, the sacrificial layer is etched back. Since the etching rate of the sacrificial layer is the same as or lower than the isolation layer within the trench, the formation of the micro-scratch is suppressed during the etching back process.

REFERENCES:
patent: 5189501 (1993-02-01), Kawamura et al.
patent: 5516729 (1996-05-01), Dawson et al.
patent: 5915175 (1999-06-01), Wise
patent: 5937308 (1999-08-01), Gardner et al.
patent: 5981354 (1999-11-01), Spikes et al.

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