Method of fabricating shallow trench insolation

Details Method of fabricating shallow trench insolation Method of fabricating shallow trench insolation

1999-09-14

2001-01-09

Saadat, Mahshid (Department: 2815)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S296000, C438S436000, C438S626000, C438S692000, C438S693000

Reexamination Certificate

active

06171928

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88113866, filed Aug. 13, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating isolation for an integrated circuit (IC) device. More particularly, the present invention relates to a method of fabricating shallow trench isolation (STI).
2. Description of Related Art
A complete circuit such as an integrated circuit (IC) is usually composed of thousands of MOS transistors. To prevent a short circuit between these adjacent transistors, an isolation structure for electrical isolation between adjacent transistors must be added.
Field oxide (FOX), manufactured by local oxidation silicon (LOCOS), is used conventionally as an isolation structure in the semiconductor process. However, there are still many issues within the LOCOS technique, including conventional problems related to the stress mechanism, the formation of a bird's beak around a LOCOS field isolation structure, etc. The problem resulting from the bird's beak, in particular, has made the LOCOS field isolation structure ineffective for isolation in small devices.
To accommodate the tendency towards shrinkage of the critical dimension (CD) of devices, shallow trench isolation, effective for isolation in small devices, has become the preferred isolation technique for the deep sub-micron process.
FIGS. 1A through 1C
are schematic, cross-sectional views showing the progression of manufacturing steps in fabricating a conventional shallow trench isolation.
First, as shown in
FIG. 1A
, a substrate
100
is provided. A pad oxide layer
102
and a mask layer
104
are sequentially formed thereon. Next, a photolithographic and etching operation is conducted to form a shallow trench
106
that extends into the substrate
100
. The pad oxide layer
102
can be formed using a thermal oxidation method and the mask layer
104
can be formed using a chemical vapor deposition (CVD) method.
A liner oxide layer
108
is then formed on the exposed surface of the substrate
100
in the shallow trench
106
. The liner oxide layer
108
can be formed using a thermal oxidation method
Referring to
FIG. 1B
, an oxide layer
110
is formed on the substrate
100
to fill the shallow trench
106
. The oxide layer
110
can be formed by first forming an oxide layer (not shown in the figure) over the mask layer
104
and filling the shallow trench
106
. Next, a chemical mechanical polishing (CMP) process is introduced to remove the oxide layer above the mask layer
104
.
The oxide layer
110
is formed by, for example, chemical vapor deposition with a gas source of ozone (O
3
) and tetra-ethyl-ortho-silicate (TEOS), or by high density plasma chemical vapor deposition (HDPCVD).
Referring to
FIG. 1C
, the pad oxide layer
102
and the mask layer
104
are removed by wet etching, and a STI is completed.
However, since different methods are used to form the pad oxide layer
102
and the oxide layer
110
, respectively, the pad oxide layer
102
and the oxide layer
110
have different densities.
In general, the pad oxide layer
102
formed by thermal oxidation has a better etching resistance than the oxide layer
110
formed by chemical vapor deposition. That is, the etching rate for the pad oxide layer
102
is lower than that for the oxide layer
110
in the same etching process. Thus, in the prior art, when the pad oxide layer
102
and the oxide layer
110
are removed in an etching process, the oxide layer
110
in the STI
106
is more easily etched than the pad oxide layer
102
does. Thus, a cavity
112
is formed on the surface of the oxide layer
110
in the vicinity of the interface between the STI
106
and the substrate
100
.
Due to the cavity
112
in the oxide layer
110
that fills the STI
106
, a kink effect is induced during the operation of the device. Thus, the isolation of the STI may malfunction because of a significant subthreshold current, and the yield could be reduced.
SUMMARY OF THE INVENTION
The invention provides a fabrication of a shallow trench isolation to prevent an oxide layer in the vicinity of the interface between a substrate and a STI from forming a cavity while a pad oxide layer is removed, to prevent a kink effect from being induced during the operation of a device, and further to prevent a reduction in yield.
According to the invention, the fabrication comprises providing a substrate, on which a pad oxide layer and a mask layer are formed. The pad oxide layer is formed by thermal oxidation. Photolithography and etching operation are next performed to form an STI in the substrate. A liner oxide layer is then formed on the substrate around the STI and an oxide layer is formed by chemical vapor deposition to cover the mask layer and to fill the STI. Portions of the oxide layer on the surface of the mask layer and remaining portions of the oxide layer in the STI are removed, followed by removal of the mask layer and the pad oxide layer and resulting in a cavity in the oxide layer in the vicinity of an interface between the STI and the substrate. A spin-on glass layer is formed on the resulting structure to fill the cavity, and is planarized to expose the substrate and the spin-on glass layer remaining in the cavity. The spin-on glass layer in the cavity is annealed and becomes an oxide layer.
The invention forms a spin-on glass layer after removing a pad oxide layer in a STI process in order to fill a cavity formed in an oxide layer in the vicinity of an interface between a STI and a substrate, performs a planarization process, and anneals the spin-on glass layer into an oxide layer with good thermal stability.
The invention provides a spin-on glass layer with a good capability for filling a cavity to reduce a kink effect resulting from the cavity. Thus, the phenomenon of increasing a subthreshold current is minimized during the operation of a device, and a yield is enhanced.
The invention provides a slurry with a higher polishing rate of a spin-on glass layer with respect to an oxide layer formed by chemical vapor deposition for planarizing the spin-on glass layer in a chemical mechanical polishing process. As a result, dishing is minimized on the surface of the oxide layer in the STI structure, and the process window is enhanced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5246884 (1993-09-01), Jaso et al.
patent: 5872043 (1999-02-01), Chen
patent: 5932487 (1999-08-01), Lou et al.
patent: 5950090 (1999-09-01), Chen et al.
patent: 6008108 (1999-12-01), Huang et al.
patent: 98-119433 (1997-11-01), None

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