Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Patent
1998-03-25
2000-11-21
Chaudhuri, Olik
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
438278, H01L 2182, H01L 218236
Patent
active
061501980
ABSTRACT:
A semiconductor read-only memory (ROM) device is provided. The particular semiconductor structure of this ROM device can reduce the parasitic capacitance between the bit lines and the word lines, such that the resistance-capacitance time constant of the memory cells can be reduced to thereby speed up the access time of the read operation to the memory cells. The binary data stored in each memory cell is dependent on whether one contact window is predefined to be formed in a thick insulating layer between the buried bit lines and the overlaying word lines. If the gate electrode of one memory cell is electrically connected to the associated word line via one contact window through the insulating layer, that memory cell is set to a permanently-ON state representing a first binary value; otherwise, that memory cell is set to a permanently-OFF state representing a second binary value.
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Chaudhuri Olik
Coleman William David
United Microelectronics Corp.
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