Method of fabricating semiconductor element having lightly doped

Details Method of fabricating semiconductor element having lightly doped Method of fabricating semiconductor element having lightly doped

1992-01-13

1992-11-24

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 27, 437 28, 437 29, 437 56, 437 34, H01L 21265

Patent

active

051660873

ABSTRACT:
A method of fabricating an insulating gate type field-effect transistor in which a region having a low carrier density for mitigating electric field is provided so as to abut on a source/drain region having a high carrier density, the method comprising the steps of: forming a gate insulating film and a gate electrode on a semiconductor substrate; depositing an insulating thin film on the gate electrode and the gate insulating film to a vertical thickness; and performing from above the insulating thin film, ion implantation at an implantation energy inducing a projected range of ions approximately equal to the vertical thickness of the insulating thin film so as to form the source/drain region; wherein a horizontal thickness of the insulating thin film on opposite sides of the gate electrode is larger than a sum of a lateral diffusion distance of the source/drain region at the time of the ion implantation and a lateral diffusion distance of the source/drain region after the ion implantation.

REFERENCES:
patent: 4843023 (1989-06-01), Chiu et al.
patent: 5015595 (1991-05-01), Wollesen
patent: 5036019 (1991-07-01), Yamane et al.
patent: 5073514 (1991-12-01), Ito et al.

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