Method of fabricating semiconductor devices using shallow...

Details Method of fabricating semiconductor devices using shallow... Method of fabricating semiconductor devices using shallow...

1999-10-25

2001-09-04

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S425000, C438S433000, C438S435000

Reexamination Certificate

active

06284623

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to fabricating semiconductor devices, and more particularly, to fabricating semiconductor devices using Shallow Trench Isolation (“STI”) with pad nitride pull-back and transistor edge self-aligned implant to reduce reverse narrow channel effect (“RNCE”).
2. Description of the Related Art
In general, semiconductor devices are manufactured or fabricated on disks of semiconductor materials called wafers or slices. More particularly, with reference to
FIG. 1
, a cross section of a portion of a typical semiconductor wafer
100
utilized in fabricating semiconductor devices is shown. Semiconductor wafer
100
may include a substrate layer
102
, a silicon dioxide layer
104
, and a nitride layer
106
.
Over the years, the number of semiconductor devices which may be formed on a single semiconductor wafer
100
has continuously increased with the corresponding reduction in the size of the semiconductor devices. In fact, the fabrication of semiconductor devices with device pitch sizes (i.e., the smallest dimension of a device with isolation) at a sub-micron (i.e., less than 1 micron) and a sub-half micron scale has been made possible with the advent of Shallow Trench Isolation (“STI”) techniques.
With reference to
FIG. 2
, a conventional STI technique may be utilized to form trenches (also known as gaps)
110
and mesas (which include active regions)
112
on a semiconductor wafer
100
. More particularly, gaps
110
are etched with the nitride layer
106
of
FIG. 1
as a hard mask, then filled in with an oxide layer
107
(commonly known as a field oxide layer). Semiconductor wafer
100
then undergoes chemical mechanical planarization (“CMP”) to produce a smooth and planar surface. After the nitride mask is removed and wafer surface is cleaned, a very thin layer of oxide (i.e., gate oxide) is grown. A poly-silicon (also known as ‘poly’) layer
108
is then deposited.
Conventional STI techniques, however, produce active regions
112
with sharp corners
116
and divots
114
in the field oxide layer
107
. Additionally, conventional STI techniques result in dopant loss at edges
118
of active regions
112
. Consequently, semiconductor devices fabricated using conventional STI techniques typically suffer from Reverse Narrow Channel Effect (“RNCE”), which is characterized by a low threshold voltage (i.e., the voltage at which the device turns on) and a high off-current (i.e., the current at which the device turns off). In general, semiconductor devices with high off-currents are undesirable as they require more power and cannot be effectively turned off.
SUMMARY OF THE INVENTION
The present invention relates to fabricating semiconductor devices such as conductors, fuses, capacitors, diodes, transistors, and the like. In accordance with an exemplary embodiment of the present invention, a semiconductor wafer having a substrate material, an oxide layer, and a nitride layer is either formed or obtained. Mesas (the edges of which comprise active regions) are then formed by etching trenches (gaps) into the substrate material through the nitride and oxide layers. In accordance with one aspect of the present invention, the nitride layer is then pulled-back or retracted from the edges of the active regions thus exposing the corners of the active regions. The gaps and the edges of the active regions are then lined with a layer of oxide which rounds the corners of the active regions. The gaps are filled with another layer of oxide, and the semiconductor wafer is then planarized. In accordance with another aspect of the present invention, the edges of the active regions are then implanted with dopant.


REFERENCES:
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patent: 5960276 (1999-09-01), Liaw et al.
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Scott Williams, “In-Situ Nitride Mask Open,” IEEE/CPMT: Twenty-Third Electronics Manufacturing Technology Symposium, Oct. 1998, pp. 146-149.

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