Method of fabricating semiconductor devices having a diffused re

Details Method of fabricating semiconductor devices having a diffused re Method of fabricating semiconductor devices having a diffused re

1984-09-12

1986-02-04

Ozaki, George T.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29580, 357 22, 148187, H01L 21441, H01L 21465

Patent

active

045676410

ABSTRACT:
An improved semiconductor device having a diffused region of reduced length and an improved method of fabricating such a semiconductor device are disclosed. The semiconductor device may be a MOSFET or an IGR, by way of example. In a form of the method of fabricating a MOSFET, an N.sup.+ SOURCE is diffused into a P BASE through a window of a diffusion mask. An anisotropic or directional etchant is applied to the N.sup.+ SOURCE through the same window. The etchant removes most of the N.sup.+ SOURCE, but allows shoulders thereof to remain intact. These shoulders, which form the completed N.sup.+ SOURCE regions, are of reduced length, greatly reducing the risk of turn-on of a parasitic bipolar transistor in the MOSFET. The risk of turn-on of a parasitic bipolar transistor in an IGR is similarly reduced, when the IGR is fabricated by the improved method.

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patent: 4374455 (1983-02-01), Goodman
patent: 4430792 (1984-02-01), Temple
patent: 4476622 (1984-10-01), Cogan
patent: 4497109 (1985-02-01), Huber et al.
patent: 4503598 (1985-03-01), Vora et al.

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