Semiconductor device manufacturing: process – Having diamond semiconductor component
Reexamination Certificate
1999-08-17
2002-10-08
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Having diamond semiconductor component
C438S122000
Reexamination Certificate
active
06461889
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same and more particularly, to a method of fabricating a semiconductor device equipped with a diamond substrate and a device structure such as a Gallium Arsenide (GaAs) Field-Effect Transistor (FET) or FETs and a method of fabricating the semiconductor device, which provides improvement in heat dissipation performance.
2. Description of the Prior Art
With high-output semiconductor devices, a lot of heat is generated in the devices on operation and therefore, the output level lowering and/or the reliability degradation tend to occur due to the heat. The devices themselves may be damaged due to the heat. In particular, since GaAs has a higher thermal resistance than that of silicon (Si), GaAs FETs have a low heat dissipation performance than Si FETs. Thus, to improve the performance of high-output GaAs devices, it is essential to make the heat dissipation performance as high as possible.
The Japanese Non-Examined Patent Publication No. 5-166899 published in 1993 discloses a semiconductor device of this sort, which is shown in FIG.
1
.
The prior-art semiconductor device of
FIG. 1
is comprised of a semi-insulating GaAs substrate
600
polished to have a thickness of 30 &mgr;m. An n-type active layer
601
is formed in the surface area of the GaAs substrate
600
. On the surface area of the substrate
600
, a source electrode
602
a,
a drain electrode
602
b,
and a gate electrode
603
are formed. The source electrode
602
a
is located to overlap with one end of the active layer
601
. The drain electrode
602
b
is located to overlap with the other end of the active layer
601
. The gate electrode
603
is located approximately in the middle of the active layer
601
. The active layer
601
, the source and drain electrodes
602
a
and
602
b,
and the gate electrode
603
constitute a GaAs FET structure
609
.
A lot of grooves
608
, each of which has a depth of 2 &mgr;m and a width of 2 &mgr;m, are formed on the back surface of the GaAs substrate
600
by etching to overlap with the whole active layer
601
, thereby increasing the surface area of the back surface of the GaAs substrate
600
.
A Plated Heat Sink (PHS)
607
with a thickness of 30 &mgr;m is fixed to the grooved back surface of the substrate
600
. The PHS
607
is made of gold (Au) and fixed by a plating process.
Because of the increased interface area of the GaAs substrate
600
and the PHS
607
, the heat dissipation performance of the semiconductor device of
FIG. 1
is enhanced without changing the dimension or size of the device.
However, the above-described prior-art semiconductor device of
FIG. 1
has a problem that the temperature at the interface of the substrate
600
and the PHS
607
is scarcely changed. This problem is caused by the fact that the thickness of the GaAs substrate
600
is scarcely changed although the contact area of the substrate
600
and the PHS
607
is increased by formation of the grooves
608
to thereby enhance the thermal conductivity and the heat dissipation effect.
This point is explained in detail below.
Here, the area of the channel region of the FET structure
609
is defined as A
1
and it is supposed that all the heat generated in the channel region is propagated to the PHS
607
. Then, the thermal flux Q
1
of the GaAs substrate
600
per unit time in the steady state is expressed by the following equation (1)
Q
1
=
k
1
(
θ
1
-
θ
)
A
1
δ
1
(
1
)
where k
1
is the thermal conductivity of the substrate
600
, &dgr;
1
is the thickness of the substrate
600
, &thgr;
1
is the temperature of the heat source (i.e., the channel region), and &thgr; is the temperature at the interface of the substrate
600
and the PHS
607
.
The thermal flux Q
2
of the PHS
607
per unit time in the steady state is expressed by the following equation (2)
Q
2
=
k
2
(
θ
-
θ
2
)
A
2
δ
2
(
2
)
where A
2
is the area of the interface of the substrate
600
and the PHS
607
, k
2
is the thermal conductivity of the PHS
607
, &dgr;
2
is the thickness of the PHS
607
, and &thgr;
2
is the temperature at the outer surface of the PHS
607
contacting with the atmosphere.
When the thermal conductivity, the thickness, and the cross-sectional area of a material are defined as k, &dgr;, and A, respectively, the thermal resistance R of the material is generally given by
R
=
δ
kA
(
3
)
Therefore, the following equations (4) and (5) are established.
R
1
=
δ
1
k
1
A
1
(
4
)
R
2
=
δ
2
k
2
A
2
(
5
)
Therefore, by using the equations (4) and (5), the above-described equations (1) and (2) are rewritten to as follows.
Q
1
=
θ
1
-
θ
R
1
(
1
′
)
Q
2
=
θ
-
θ
2
R
2
(
2
′
)
Considering the flow of heat in the steady state, Q
1
=Q
2
is established. Also, it is supposed that the substrate
600
and the PHS
607
are equal in thickness and area to each other, the temperature &thgr; at the substrate-PHS interface is given as a function of the thermal conductivities k
1
and k
2
and temperatures &thgr;
1
and &thgr;
2
as follows.
θ
=
k
1
θ
1
+
k
2
θ
2
k
1
+
k
2
(
6
)
When &thgr;
1
=100° C., &thgr;
2
=40° C., k
1
=0.46 W/cm° C., and k
2
=3.2 W/cm° C., the equation (6) gives &thgr;=47.5° C.
The above explanation is applied to the case where the grooves
608
are omitted in the prior-art semiconductor device of FIG.
1
. On the other hand, with the prior-art semiconductor device of
FIG. 1
having the grooves
608
, the temperature &thgr; at the interface of the substrate
600
and the PHS
607
is given as follows.
It is supposed that the contact area A
m
of the substrate
600
and the PHS
607
is twice as much as that of the above-described case where the grooves
608
are omitted (i.e., A
m
=2A
1
) while the area A
1
of the channel region is unchanged. Then, the thermal conduction from the area A
1
to the area A
m
(=2A
1
) is approximated to the planar conduction model of heat by using the logarithmically averaging conversion method, resulting in the following equation (7)
Q
1
=
k
1
(
θ
1
-
θ
)
A
m
δ
1
(
7
)
where the area A
m
is given by the following expression (8).
A
m
=
A
1
ln
(
2
)
≅
1.44
A
1
(
8
)
It is supposed that the PHS
607
has a heat dissipation area twice as much as that of the area A
1
. Then, the following equation (9) is obtained.
Q
2
=
k
2
(
θ
-
θ
2
)
2
A
1
δ
2
(
9
)
Since Q
1
=Q
2
is established in the steady state, the following equation (10) is obtained.
θ
=
1.44
k
1
θ
1
+
2
k
2
θ
2
1.44
k
1
+
2
k
2
(
10
)
When &thgr;
1
=100° C., &thgr;
2
=40° C., k
1
=0.46 W/cm° C., and k
2
=3.2 W/cm° C., which is the same condition as that of the above-described equation (6), the equation (10) gives &thgr;=45.6° C.
As seen from this result, even if the interface area (or contact area) of the GaAs substrate
600
and the PHS
607
is twice as much as that of the case where the grooves
608
are omitted, the temperature &thgr; at the substrate-PHS interface is decreased by only approximately 2° C. In other words, the temperature lowering rate (i.e., temperature gradient) in the GaAs substrate
600
is as low as 1.81° C./&mgr;m.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention to provide a semiconductor device having a decreased thermal resistance and a method of fabricating the semiconductor device.
Another object of the present invention to provide a semiconductor device having an improved heat dissipation performance and a method of fabricating the semiconductor device.
Still another object of the present invention to provide a semiconductor device having an improved radio-frequency (RF) characteristics and a method of
Le Thao Phuong
NEC Corporation
Nelms David
LandOfFree
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