Method of fabricating semiconductor device with a gate-side air-

Details Method of fabricating semiconductor device with a gate-side air- Method of fabricating semiconductor device with a gate-side air-

1998-04-07

2000-01-18

Bowers, Charles

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having air-gap dielectric

438586, 438595, 438585, 438197, 438199, 438299, 438301, 438303, H01L 213205, H01L 214763

Patent

active

060157461

ABSTRACT:
A method of fabricating a semiconductor device. On a semiconductor substrate comprising a device isolation structure and an active region isolated by the device isolation region, an oxide layer is formed and etched on the active region to form an opening, so that the active within the opening is exposed. A first spacer is formed on a side wall of the opening. A gate oxide layer is formed on the active region within the opening. A conductive layer is formed on the gate oxide layer, so that the opening is filled thereby. The oxide layer is removed. The exposed active region is lightly doped to form a lightly doped region by using the conductive layer and the first spacer as a mask. A second spacer is formed on a side wall of the first spacer and leaves a portion of the first spacer to be exposed. The exposed active region is heavily doped to form a source/drain region by using the conductive layer, the first spacer, and the second spacer as a mask. The first spacer is removed to define a gate, so that an air gap between the gate and the second spacer is formed.

REFERENCES:
patent: 5668021 (1997-09-01), Subramanian et al.
patent: 5786256 (1998-07-01), Gardner et al.
M. Togo, "A Gate-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance in MOFET's", 1996 Symposium on VLSI Technology Digest of Technician Practice, pp. 38-39, Jul. 1996.

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