Method of fabricating semiconductor device having sidewall space

Details Method of fabricating semiconductor device having sidewall space Method of fabricating semiconductor device having sidewall space

1991-10-24

1993-06-08

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 30, 437 44, 437149, H01L 21265

Patent

active

052179109

ABSTRACT:
First, a low-concentration impurity layer is formed by obliquely implanting an n-type impurity at a prescribed angle with respect to the surface of a p-type semiconductor substrate, using a gate electrode formed on the semiconductor substrate as a mask. Thereafter a sidewall spacer is formed on the sidewall of the gate electrode, and then a medium-concentration impurity layer is formed by obliquely implanting an n-type impurity to the surface of the semiconductor substrate. Thereafter a high-concentration impurity layer is formed by substantially perpendicularly implanting an n-type impurity with respect to the surface of the semiconductor substrate. According to this method, the low-concentration impurity layer in source and drain regions having triple diffusion structures can be accurately overlapped with the gate electrode, with no requirement for heat treatment for thermal diffusion.

REFERENCES:
patent: 4771012 (1988-09-01), Yabu et al.
patent: 4843023 (1989-06-01), Chiu et al.
patent: 4891326 (1990-01-01), Koyanagi
patent: 4978626 (1990-12-01), Poon et al.
"Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology", IEEE Transactions on Electron Devices, vol. ED-29, No. 4, Apr., 1982, by Paul J. Tsang et al, pp. 590-596.

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