Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1998-07-29
2001-10-09
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S003000
Reexamination Certificate
active
06300212
ABSTRACT:
BACKGROUND OF THE INVENTION
(i) Field of the Invention
The present invention relates to method of fabricating a semiconductor device, particularly to a method of fabricating a semiconductor memory device having a memory capacitor including a dielectric layer is made of a composite metal oxide.
(ii) Description of the Related Art
It is prevalent to develop semiconductor memory devices in which ferroelectric thin films made of composite metal oxides or thin films having high dielectric constant capacities made of composite metal oxides are used for the dielectric layers of memory capacitors. With miniaturization of semiconductor devices in recent years, it becomes an issue how small area the necessary capacitance of each memory capacitor is ensured by in a dynamic random access memory (DRAM) for instance. One of solutions of this problem is a method that the dielectric substance used as the dielectric layer of each memory capacitor is changed from conventional silicon oxide, silicon nitride or the like to a substance having a higher dielectric constant capacitance. It is expected that substances having high dielectric constant capacities such as SrTiO
3
or ferroelectric substances such as Pb(Zr,Ti)O
3
(hereinafter, called PZT) are useful for this purpose.
Besides, when a ferroelectric substance is used for the dielectric layer of each memory capacitor, a new function of non-volatility can be added to the semiconductor memory device. The dielectric layer of the ferroelectric substance has the following characteristic. When a voltage is applied to polarize the dielectric layer, the polarization does not become zero and remains even after stopping applying the voltage. By utilizing the remaining polarization, the memory device including the dielectric layer of the ferroelectric substance can be used as a non-volatile memory. The basic structure of such a ferroelectric non-volatile memory includes a MOS field effect transistor (MOSFET) and a ferroelectric capacitor in each memory cell. It has many common points in structure and manufacturing method with a general dynamic memory. Hereinafter, prior arts of the nonvolatile memories using ferroelectric substances will be described.
The structures and manufacturing methods of conventional ferroelectric memory devices are as follows.
FIG. 16
shows the structure of a conventional ferroelectric memory device disclosed by Japanese Patent Opening No. 80959/1992. As shown in
FIG. 16
, a MOS transistor comprises a gate electrode
15
and diffusion layers
16
in a region separated by a LOCOS insulator
24
on a silicon substrate
11
. A ferroelectric capacitor comprises a lower electrode
18
made of platinum (Pt), a ferroelectric layer
19
and an upper electrode
27
made of aluminum (Al). The ferroelectric capacitor is electrically connected to one of the diffusion layers
16
of the MOS transistor through a titanium silicide layer
25
. The ferroelectric layer
19
is made of PbTiO
3
, PZT, (Pb,La)(Zr,Ti)O
3
(hereinafter, called PLZT) or the like. The transistor part, the capacitor part and wiring parts are insulated from one another by an inter-layer insulator
13
comprising two layers of silicon oxides for instance.
The ferroelectric memory of this first prior art is generally manufactured by the following process. First, the transistor is formed by the conventional manner in the region separated by the LOCOS insulator
24
on the silicon substrate
11
and the lower inter-layer insulator
132
is formed thereon. Successively, a part of the lower inter-layer insulator
132
is opened to expose one of the diffusion layers
16
of the transistor in the opening. The ferroelectric capacitor is formed on the opening portion of the lower inter-layer insulator
132
to be electrically connected to the transistor. In this prior art, a titanium layer
26
is formed in the opening and then a thermal treatment is performed. By this manner, the part of the titanium layer
26
contacting the diffusion layer
16
is silicified to obtain the titanium silicide layer
25
. This is for lowering the contact resistance between the diffusion layer of the transistor and the electrode of the capacitor to be formed thereon. Next, a Pt layer to form the lower electrode
18
and, for instance, a PZT layer to form the ferroelectric layer
19
are formed in order on the titanium silicide layer
25
. In this prior art, these are both formed by sputtering methods. Successively, the Pt layer and the PZT layer are patterned by a photolithographing and etching process to obtain the lower electrode
18
and the ferroelectric layer
19
. After forming the upper inter-layer insulator
131
, a part of it is opened by an etching process using plasma to expose the ferroelectric layer
19
in the opening. An aluminum (Al) layer is formed by sputtering so as to fill up the opening and thereby an aluminum wiring layer
27
combining the upper electrode
20
and a bit line is obtained.
As the second prior art, a ferroelectric memory device constructed as shown in
FIG. 17
is used (Japanese Patent Opening No. 79266/1992). In the prior art shown in
FIG. 17
, a ferroelectric capacitor comprising a lower electrode
18
, a ferroelectric layer
19
and an upper electrode
20
is formed at a position distant from the just upper position of a diffusion layer
16
of a transistor. The ferroelectric capacitor is electrically connected to the diffusion layer
16
through a wiring metal layer
22
.
The manufacturing process of the prior art shown in
FIG. 17
is as follows. The transistor
14
is formed on a silicon substrate
11
by a conventional manner. An inter-layer insulator
13
of, for instance, silicon oxide is formed. A Pt layer is first formed on the inter-layer insulator
13
by sputtering and then patterned by a photolithographing and etching process so that it remains only in a predetermined region in which the capacitor is to be formed. The lower electrode
18
is thereby formed. Similarly, a ferroelectric layer is formed on the whole area and then patterned by a photolithography process so that it remains only in the region required for forming the capacitor. The ferroelectric layer
19
is thereby formed. The ferroelectric layer
19
is then treated with heat to crystallize. The reason why the thermal treatment is performed after patterning is as follows. It becomes possible to control to the minimum the stress due to the shrinkage of the volume of the layer upon crystallization and the exfoliation of the ferroelectric layer does not occur. After that, another Pt layer is formed by sputtering and then patterned by a photolithography process so that it remains only in the region first formed on the inter-layer insulator
13
by sputtering and then patterned by a photolithographing and etching process so that it remains only in the region required for forming the capacitor. The upper electrode
20
is thereby formed. At the last, a part of the inter-layer insulator
13
is opened to expose the diffusion layer of the transistor. An aluminum layer is formed on the inter-layer insulator
13
including the opening portion and then patterned into a predetermined shape to obtain the wiring layer.
But the conventional manufacturing methods of the semiconductor devices including the ferroelectric capacitors have the following problem. There is a deterioration in reliability due to a contamination of the ferroelectric layer and a change of the composition thereof.
In the conventional manufacturing methods including the above examples, it is general to form the lower electrode, ferroelectric layer and upper electrode constituting the ferroelectric capacitor in separate apparatus. In this manner, for instance, the substrate on which the ferroelectric layer had been formed in an apparatus for forming the ferroelectric layer is once taken out in the air and then put in an apparatus for forming the upper electrode. Accordingly, the ferroelectric layer is inevitably exposed to the air between both stages so the surface of the ferroelectric layer is contaminated with floating matters
Hayashi Yoshihiro
Inoue Naoya
Foley & Lardner
NEC Corporation
Nelms David
Nhu David
LandOfFree
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