Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal – Responsive to electromagnetic radiation
Reexamination Certificate
2011-03-15
2011-03-15
Everhart, Caridad M (Department: 2895)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
Responsive to electromagnetic radiation
C438S067000, C257SE21513, C257SE21606
Reexamination Certificate
active
07906363
ABSTRACT:
A method of fabricating a semiconductor device having a three-dimensional stacked structure by stacking semiconductor circuit layers on a support substrate, including the steps of: forming a trench in a semiconductor substrate; filling inside the trench with a conductive material to form a conductive plug; forming an element or circuit in an inside or on a surface of the semiconductor substrate where the conductive plug was formed; covering the surface of the semiconductor substrate where the element or circuit was formed with a second insulating film; and fixing the semiconductor substrate to the support substrate or a remaining one of the semiconductor circuit layers by joining the second insulating film to the support substrate or the remaining one of the semiconductor circuit layers through a wiring structure; selectively removing the semiconductor substrate to expose the first insulating film; and selectively removing the first insulating film.
REFERENCES:
patent: 4939568 (1990-07-01), Kato et al.
patent: 5846879 (1998-12-01), Winnerl et al.
patent: 6025648 (2000-02-01), Takahashi et al.
patent: 6624081 (2003-09-01), Dykstra et al.
patent: 6677235 (2004-01-01), Yegnashankaran et al.
patent: 6936532 (2005-08-01), Sakaida
patent: 7564118 (2009-07-01), Pogge et al.
patent: 2003/0193076 (2003-10-01), Patti
patent: 2003/0222343 (2003-12-01), Sakaida
patent: 2006/0124927 (2006-06-01), Groves et al.
patent: 2009/0215261 (2009-08-01), Kawano
patent: 60-7149 (1985-01-01), None
patent: 62-272556 (1987-11-01), None
patent: 02-278893 (1990-11-01), None
patent: 03-276750 (1991-12-01), None
patent: 04-326757 (1992-11-01), None
patent: 8-509842 (1996-10-01), None
patent: 10-189653 (1998-07-01), None
patent: 11-238870 (1999-08-01), None
patent: 2000-326326 (2000-11-01), None
patent: 2001-057404 (2001-02-01), None
patent: 2001-274196 (2001-10-01), None
patent: 2001-326325 (2001-11-01), None
patent: 2001-326326 (2001-11-01), None
patent: 2002-110902 (2002-04-01), None
patent: 2002-513208 (2002-05-01), None
patent: 2002-289623 (2002-10-01), None
patent: 2003-124251 (2003-04-01), None
patent: 2004-014657 (2004-01-01), None
Kurino, K., et al., “Intelligent Image Sensor Chip with Three Dimensional Structure,” IEEE, 1999, pp. 879-882.
Lee, Kang Wook, et al., “Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip,” Jpn. J. Appl. Phys., vol. 39. 2000, pp. 2473-2477.
Xiong, Xiaorong et al. “Controlled Multibatch Self-Assembly of Microdevices”, Journal of Michroelectromechanical Systems, vol. 12, No. 2, pp. 117-127, Apr. 2003.
Office Action issued in co-pending related U.S. Appl. No. 11/570,009, mailed Nov. 4, 2010.
Everhart Caridad M
Griffin & Szipl, P.C.
ZyCube Co., Ltd.
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